Datasheet
78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 194
Feb 28, 2012
(2) 16-bit timer Xn operation control register 1 (TXnCTL1)
TXnCTL1 is a register that sets timer start via detection of INTP0 rising edge, output gate function by TOH1 output,
the PWM output operation, and synchronous operation mode.
TXnCTL1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TXnCTL1 to 00H.
Remark n = 0, 1
Figure 6-8. Format of 16-Bit Timer X0 Operation Control Register 1 (TX0CTL1)
Address: FF7FH After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> 2 1 0
TX0CTL1 TX0INTPST 0 TX0PWM
CE
TX0PWM
CINV
TX0PWM 0 0 0
TX0INTPST Control of timer start operation via detection of INTP0 rising edge
0
Disables timer start operation via detection of INTP0 rising edge (starts timer via setting (1) of
TX0TMC)
Note 1
.
1
Enables timer start operation via detection of INTP0 rising edge
Note 2
.
TX0PWM
CE
Control of TOX0n output gate function by TOH1 output (n = 0, 1)
0 Does not use output gate function.
1 Use output gate function.
TX0PWM
CINV
Setting of TOXmn output by TOH1 output (mn = 00, 01, 10, 11)
0 Performs PWM output from TOXmn while the TOH1 output is high level.
Outputs a default level of TOXmn while the TOH1 output is low level.
1 Performs PWM output from TOXmn while the TOH1 output is low level.
Outputs a level that is the inverse of the default level of TOXmn while the TOH1 output is high
level.
TX0PWM TMX0 PWM output operation setting
0
Single output (TOX00 pin only)
INTTMX0 is generated upon match of counter and TX0CR1 register
1
Dual output (TOX00 and TOX01 pins)
INTTMX0 is generated upon match of counter and TX0CR3 register
Notes 1. In TMX0 or TMX1 synchronous start mode, a timer start operation via detection of INTP0 rising edge
cannot be performed, so set TX0INTPST to 0.
2. If 1 is set to TX0TMC after setting 1 to TX0INTPST, detection of INTP0 rising edge will be waited for. If the
INTP0 rising edge is detected, 16-bit timer X0 will start counting up.
Caution 1. During timer operation, setting the other bits of TX0CTL1 is prohibited. However, TX0CTL1 can
be refreshed (the same value is written).