Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 193
Feb 28, 2012
Figure 6-7. Format of 16-Bit Timer X1 Operation Control Register 0 (TX1CTL0)
Address: FF94H After reset: 00H R/W
Symbol <7> 6 5 4 3 <2> <1> <0>
TX1CTL0 TX1TMC 0 0 0 0 TX1CKS2 TX1CKS1 TX1CKS0
TX1TMC TMX1 count operation control
0 Stops timer count operation (counter is cleared to 0)
1 Enables timer count operation
TMX1 count clock selection TX1
MD1
TX1
MD0
SEL
PLL
TX1
CKS2
TX1
CKS1
TX1
CKS0
fPRS = 4 MHz
f
PRS = 20 MHz
(when using PLL)
0 0 0 0 fPRS 4 MHz
0 0 0 1 fPRS/2 2 MHz
0 0 1 0
f
PRS/2
2
1 MHz
0 0 1 1
f
PRS/2
3
500 kHz
0 1 0 0
f
PRS/2
4
250 kHz
0 1 0 1
f
PRS/2
5
125 kHz
0 1 1 0
f
PRS/2
6
62.5 kHz
0 1 1 1
f
PRS/2
7
31.25 kHz
1 0 0 0
f
TMX
(fTMX = 10 fXP)
40 MHz
0 0/1
1 0 0 1 f
PRS
20 MHz
1 0 x x x x
TMX0 count clock (see Figure 6-6 Format of 16-Bit
Timer X0 Operation Control Register 0 (TX0CTL0))
Other than above Setting prohibited
Cautions 1. Only 4 MHz can be used for the PLL reference clock oscillation frequency.
2. When rewriting TX1CKS2 to TX1CKS0 bits to other data, stop the timer operation beforehand
(TX1TMC = 0).
Remark SELPLL: Bit 3 of the internal oscillation mode/PLL control register (RCM)
TX1MD1, TX1MD0: Bits 1 and 0 of the 16-bit timer X1 operation control register 1
f
PRS: Peripheral hardware clock frequency
f
TMX: TMX control clock frequency
fXP: Main system clock frequency