Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 192
Feb 28, 2012
(1) 16-bit timer Xn operation control register 0 (TXnCTL0)
TXnCTL0 is a register that controls the count operation and sets the count clock of 16-bit timer Xn.
TXnCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TXnCTL0 to 00H.
Figure 6-6. Format of 16-Bit Timer X0 Operation Control Register 0 (TX0CTL0)
Address: FF7EH After reset: 00H R/W
Symbol <7> 6 5 4 3 <2> <1> <0>
TX0CTL0 TX0TMC 0 0 0 0 TX0CKS2 TX0CKS1 TX0CKS0
TX0TMC TMX0 count operation control
0 Stops timer count operation (counter is cleared to 0)
1 Enables timer count operation
TMX0 count clock selection SELPLL TX0CKS2 TX0CKS1 TX0CKS0
f
PRS = 4 MHz
f
PRS = 20 MHz
(when using PLL)
0 0 0 0 fPRS 4 MHz

0 0 0 1 fPRS/2 2 MHz

0 0 1 0
f
PRS/2
2
1 MHz

0 0 1 1
f
PRS/2
3
500 kHz

0 1 0 0
f
PRS/2
4
250 kHz

0 1 0 1
f
PRS/2
5
125 kHz

0 1 1 0
f
PRS/2
6
62.5 kHz

0 1 1 1
f
PRS/2
7
31.25 kHz

1 0 0 0
f
TMX
(fTMX = 10 fXP)

40 MHz
1 0 0 1 fPRS

20 MHz
Other than above Setting prohibited
Cautions 1. Only 4 MHz can be used for the PLL reference clock oscillation frequency.
2. When rewriting TX0CKS2 to TX0CKS0 bits to other data, stop the timer operation beforehand
(TX0TMC = 0).
Remark SELPLL: Bit 3 of the internal oscillation mode/PLL control register (RCM)
f
PRS: Peripheral hardware clock frequency
f
TMX: TMX control clock frequency
fXP: Main system clock frequency
n = 0, 1