Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 190
Feb 28, 2012
(1) 16-bit timer Xn capture/compare register 0 (TXnCCR0)
This is a 16-bit register that can switch between being used for the capture function and the compare function.
TXnCTL2 is used to switch between the capture function and compare function.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 6-4. Format of 16-bit timer Xn capture/compare register 0 (TXnCCR0)
TXnCCR0
FF93H (TX0CCR0), FFB7H (TX1CCR0) FF92H (TX0CCR0), FFB6H (TX1CCR0)
Address: FF92H, FF93H (TX0CCR0), FFB6H, FFB7H (TX1CCR0) After reset: 0000H R/W
1514131211109876543210
(i) Using TXnCCR0 as a compare register
TXnCCR0 can be refreshed (writing the same value) and its value can be rewritten while the timer is counting
(TXnTMC = 1). When the value of TXnCCR0 is rewritten while the timer is operating, that value is latched,
transferred to TXnCCR0 at the following timing, and the value of TXnCCR0 is changed.
The counter value and TXnCR1 setting value match (TXnPWM = 0)
The counter value and TXnCR3 setting value match (TXnPWM = 1)
In interlocking mode 2, the latched value is transferred to TXnCCR0 and the value of TXnCCR0 is changed at the
timing of the comparator output by setting the TX0CMPLDSET1 and TX0CMPLDSET0 bits.
(ii) Using TXnCCR0 as a capture register
The count value is captured to TXnCCR0 by inputting a capture trigger.
Caution When reading TXnCCR0 continuously, wait for at least 3 clock cycles of the 16-bit timer Xn
count clock between reads.
Remark n = 0, 1
(2) 16-bit timer Xn compare register m (TXnCRm)
TXnCRm can be refreshed (writing the same value) and its value can be rewritten while the timer is counting
(TXnTMC = 1). When the value of TXnCRm is rewritten while the timer is operating, that value is latched, transferred
to TXnCRm at the following timing, and the value of TXnCRm is changed.
The counter value and TXnCR1 setting value match (TXnPWM = 0)
The counter value and TXnCR3 setting value match (TXnPWM = 1)
In interlocking mode 2, the latched value is transferred to TXnCRm and the value of TXnCRm is changed at the timing
of the comparator output by setting the TX0CMPLDSET1 and TX0CMPLDSET0 bits.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.