Datasheet

78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1
R01UH0010EJ0500 Rev.5.00 186
Feb 28, 2012
CHAPTER 6 16-BIT TIMERS X0 AND X1
6.1 Functions of 16-Bit Timers X0 and X1
16-bit timers X0 and X1 are mounted onto all 78K0/Ix2 microcontroller products.
16-bit timers X0 and X1 are dedicated PWM output timers and have two outputs each, enabling the generation of up to
four PWM outputs. Complementary PWM output can also be generated to control a half-bridge circuit (2 outputs) or full-
bridge circuit (4 outputs). Also, by linking with a comparator or INTP0, PFC control and PWM output can be stopped
urgently.
16-bit timers X0 and X1 are provided with the following functions.
(1) PWM output
 A variable pulse with any duty or cycle can be output while the timer is operating.
 The default timer output level (high or low level) can be set.
(2) A/D conversion start timing signal output
The A/D conversion start timing signal can be output by using a compare register (TXnCCR0 register: n = 0, 1).
(3) Capture function
This function captures the count value to the capture register by detecting a comparator output or an external interrupt
input (INTP0).
(4) Timer start synchronization function
Up to 4 PWM outputs can be simultaneously started by combining two timer units (16-bit timers X0 and X1).
(5) Timer start/clear synchronization function
Up to 4 PWM output cycles can be synchronized by combining two timer units (16-bit timers X0 and X1).
(6) Timer output gating function (by interlocking with 8-bit timer H1)
Timer output can be gate-controlled by using the output of 8-bit timer H1 (the TOH1 output).
(7) Timer reset mode (comparator, INTP0 interlocking mode 1)
Timer output can be reset and the timer counter cleared while the comparator 0 to 2 outputs or the INTP0 input is high
level. When the comparator 0 to 2 outputs or the INTP0 input go to low level, timer output restarts.
(8) Timer restart mode (comparator, INTP0 interlocking mode 2)
Timer can be restarted upon detection of the rising edge of the comparator 0 to 2 outputs or the INTP0 input.
(9) Timer output reset mode (comparator, INTP0 interlocking mode 3)
Timer output can be reset upon detection of the rising edge of the comparator 0 to 2 outputs or the INTP0 input. The
reset status is cleared when the next timer interrupt occurs and timer output restarts.
(10) High-impedance output control function (by interlocking with comparator and INTP0)
Timer output can be made high impedance upon detection of the valid edge of the comparator 0 to 2 outputs or the
INTP0 input.