Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 185
Feb 28, 2012
5.6.7 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-8. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1
(The CPU is operating on the high-speed system clock)
RSTOP = 1
X1 clock
External main system clock
MCS = 0
(The CPU is operating on the internal high-speed oscillation clock)
MSTOP = 1
5.6.8 Peripheral hardware and source clocks
T
he following lists peripheral hardware and source clocks incorporated in the 78K0/Ix2 microcontrollers.
Remark The peripheral hardware depends on the product. Refer to 1.4 Block Diagram and 1.5 Outline of
Functions.
Table 5-9. Peripheral Hardware and Source Clocks
Source Clock
Peripheral Hardware
Peripheral Hardware
Clock (f
PRS)
Internal Low-Speed
Oscillation Clock (fIL)
TMX control clock
(fTMX)
External Clock from
Peripheral Hardware
Pins
16-bit timers X0 and X1 Y N Y N
16-bit timer/event counter 00 Y N N Y (TI000 pin)
Note
8-bit timer/event counter 51 Y N N Y (TI51 pin)
Note
8-bit timer H1 Y Y N N
Watchdog timer N Y N N
A/D converter Y N N N
UART6/
DALI
Y N N N
CSI11 Y N N Y (SCK11 pin)
Note
Serial interface
IICA Y N N Y (SCLA0 pin)
Note
Note Do not start the peripheral hardware operation with the external clock from peripheral hardware pins when in
the STOP mode.
Remark Y: Can be selected, N: Cannot be selected