Datasheet
78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 183
Feb 28, 2012
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/3)
(7) HALT mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
HALT mode (I) set while CPU is operating with high-speed system clock (C)
HALT mode (F) set while CPU is operating with internal high-speed oscillation clock (PLL mode) (D)
HALT mode (G) set while CPU is operating with high-speed system clock (PLL mode) (E)
Status Transition Setting
(B) (H)
(C) (I)
(D) (F)
(E) (G)
Executing HALT instruction
(8) STOP mode (J) set while CPU is operating with internal high-speed oscillation clock (B)
STOP mode (K) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition Setting
(B) (J)
(C) (K)
Stopping peripheral functions that
cannot operate in STOP mode
Executing STOP instruction
Caution When transitioning to the STOP mode, it is possible to achieve low power consumption by setting
RMC = 56H.
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-14.
5.6.5 Condition before changing CPU clock and processing after changing CPU clock
Cond
ition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-5. Changing CPU Clock
CPU Clock
Before Change After Change
Condition Before Change Processing After Change
X1 clock Stabilization of X1 oscillation
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization
time
Internal high-speed oscillator can be
stopped (RSTOP = 1).
Internal high-speed
oscillation clock
External main
system clock
Enabling input of external clock from
EXCLK pin
MSTOP = 0, OSCSEL = 1, EXCLK = 1
Internal high-speed oscillator can be
stopped (RSTOP = 1).
X1 clock
X1 oscillation can be stopped (MSTOP = 1).
External main system
clock
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
RSTOP = 0
External main system clock input can be
disabled (MSTOP = 1).