Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 182
Feb 28, 2012
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/3)
(4) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
RSTOP RSTS MCM0
(C)  (B) 0 Confirm this flag is 1. 0
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
(5) CPU clock changing from internal high-speed oscillation clock (B) to internal high-speed oscillation clock
(PLL mode) (D)
CPU clock changing from high-speed system clock (C) to high-speed system clock (PLL mode) (E)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
SELPLL PLLON
Waiting for
Oscillation
Stabilization
SELPLL
(B)  (D)
(C)  (E)
0 1 Necessary
(90
 s)
1
Unnecessary if
these registers
are already set
Unnecessary if the CPU is operating
with the PLL
(6) CPU clock changing from internal high-speed oscillation clock (PLL mode) (D) to internal high-speed
oscillation clock (B)
CPU clock changing from high-speed system clock (PLL mode) (E) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
SELPLL PLLON
(D)  (B)
(E)  (C)
0 0
Remarks 1. (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-14.
2. A 10
 s wait occurs as an internal stabilization wait time after PLLON = 1 is set.
3. RSTS, PLLON, SELPLL, RSTOP: Bits 7, 4, 3, and 0 of the internal oscillation mode register (RCM)
MCM0: Bit 0 of the main clock mode register (MCM)