Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 181
Feb 28, 2012
Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition SFR Register Setting
(A)  (B) SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock (B) immediately after a reset release.)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL MSTOP
OSTC
Register
XSEL MCM0
(A)  (B)  (C) (X1 clock) 0 1 0
Must be
checked
1 1
(A)  (B)  (C) (external main system clock) 1 1 0
Must not be
checked
1 1
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
(3) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL MSTOP
OSTC
Register
XSEL
Note
MCM0
(B)  (C) (X1 clock) 0 1 0
Must be
checked
1 1
(B)  (C) (external main system clock) 1 1 0
Must not be
checked
1 1
Unnecessary if these
registers are already set
Unnecessary if the CPU
is operating with the
high-speed system
clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-14.
2. EXCLK, OSCSEL: Bits 7 and 6 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)