Datasheet
78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 180
Feb 28, 2012
5.6.4 CPU clock status transition diagram
Figure 5-14 shows the CPU clock status transition diagram of this product.
Figure 5-14. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set
(Option Byte: LVISTART = 0))
Power ON
Reset release
V
DD
≥ 1.61 V (TYP.)
V
DD
≥ 2.7 V (MIN.)
V
DD
< 1.61 V (TYP.)
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
PLL: Stops
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
PLL: Stops
CPU: Operating
with internal high-
speed oscillation
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
PLL: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
PLL: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
PLL: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
PLL: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input:Operating
PLL: Stops
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
PLL: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input:
Operating
PLL:
Operating
(B)
(A)
(C)
(J)
(H)
(I)
CPU: Operating
with internal high-
speed oscillation
(PLL mode)
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: Operating
with
Internal high-
speed oscillation
→ HALT
CPU: Operating
with
Internal high-
speed oscillation
→ STOP
CPU:
Operating
with X1 oscillation
/EXCLK input
→ STOP
CPU:
Operating
with X1 oscillation
/EXCLK input
→
HALT
CPU: Operating
with X1 oscillation or
EXCLK input
(PLL mode)
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Operable
PLL:
Operating
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operating
PLL:
Operating
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Operable
PLL:
Operating
CPU: Operating
with
Internal high-
speed oscillation
(PLL mode)
→ HALT
CPU: Operating
with
X1 oscillation or
EXCLK input
(PLL mode)
→ HALT
(D)
(E)
(F)
(G)
(K)
Cautions 1. Be sure to stop the operation of the PLL before shifting to STOP mode.
2. When transitioning to the STOP mode, it is possible to achieve low power consumption by
setting RMC = 56H.
3. Be sure to stop the operation of the PLL when switching the main system clock.
4. Only 4 MHz can be used for the PLL reference clock oscillation frequency.
Remark When LVI default start function enabled is set (option byte: LVISTART = 1), the CPU clock status changes to
(A) in the above figure when the supply voltage exceeds 1.91 V (TYP.), and to (B) after reset processing (12
to 51
s).
Wait for the specified time using software or wait using the LVI function until the supply voltage rises from
1.91 V (TYP.) to 2.7 V.