Datasheet
78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 173
Feb 28, 2012
Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-
speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization
time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set
the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register
(OSTS).
Cautions 1. A voltage oscillation stabilization time (0.93 to 3.7 ms) is required after the supply voltage
reaches 1.61 V (TYP.). If the supply voltage rises from 1.61 V (TYP.) to 1.91 V (TYP.) within the
power supply oscillation stabilization time, the power supply oscillation stabilization time is
automatically generated before reset processing.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
3. Do not change the PCC register until the supply voltage exceeds 2.7 V.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software
settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing
the STOP instruction (refer to (4) in 5.6.1 Example of controlling high-speed system clock, and (3) in
5.6.2 Example of controlling internal high-speed oscillation clock).
5.6 Controlling Clock
5.6.1 Example of controlling high-speed system clock
T
he following two types of high-speed system clocks are available.
X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins.
External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as input port pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU clock and peripheral hardware clock
(4) When stopping high-speed system clock
Remark See 5.4.5 PLL (phase locked loop) when using the PLL.