Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 168
Feb 28, 2012
5.4.3 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0/Ix2 microcontrollers.
The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal
low-speed oscillation clock cannot be used as the CPU clock.
“Can be stopped by software” or “Cannot be stopped” can be selected by the option byte. When “Can be stopped by
software” is set, oscillation can be controlled by the internal oscillation mode/PLL control register (RCM).
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven
(30 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte.
5.4.4 Prescaler
T
he prescaler generates the clock to be supplied to the CPU by dividing the main system clock.
5.4.5 PLL (Phase Locked Loop)
T
he PLL can be used to multiply the internal high-speed oscillation clock or high-speed system clock.
Set as follows to use or stop the PLL.
(a) When using PLL
The PLL is set to be stopped (PLLON = 0) after reset is released. After reset is released, check the oscillation
stability of the clock to be multiplied and then set the PLL to operate (PLLON = 1)
Note
. After the PLL starts
operating, check that the PLL operation stabilization time (90
s) has elapsed in clock-through mode (SELPLL =
0) and then change the mode to PLL mode (SELPLL = 1).
To shift to STOP mode, execute the STOP instruction after making sure that the mode has been changed to
clock-through mode (SELPLL = 0) and the PLL has been stopped (PLLON = 0). To return from STOP mode,
start operating the PLL (PLLON = 1), check that the PLL operation stabilization time (90
s) has elapsed, and
then change the mode to PLL mode (SELPLL = 1).
(b) When stopping PLL
• Stop the PLL (PLLON = 0) after making sure that the mode has been switched to clock-through mode (SELPLL =
0). Do not simultaneously write 0 to the SELPLL and PLLON bits by using an 8-bit memory manipulation
instruction.
Note X1 clock: Use the oscillation stabilization time counter status register (OSTC) to check
the oscillation stabilization time.
Internal high-speed oscillator: Use bit 7 (RSTS) of the internal oscillation mode/PLL control register (RCM)
to check the accuracy of the oscillation stabilization operation.
Caution Only 4 MHz can be used for the PLL reference clock oscillation frequency.
Remarks 1. A 10
s wait occurs as an internal stabilization wait time after PLLON = 1 is set.
2. SELPLL: Bit 3 of the internal oscillation mode/PLL control register (RCM)
PLLON: Bit 4 of RCM