Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 163
Feb 28, 2012
(5) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-6. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/W
Note
Symbol 7 6 5 4 3 <2> <1> <0>
MCM 0 0 0 0 0 XSEL MCS MCM0
Selection of clock supplied to main system clock and peripheral hardware
XSEL MCM0
Main system clock (fXP) Peripheral hardware clock (fPRS)
0 0
0 1
Internal high-speed oscillation clock
(f
IH)
1 0
Internal high-speed oscillation clock
(f
IH)
1 1 High-speed system clock (fXH)
High-speed system clock (f
XH)
MCS Main system clock status
0 Operates with internal high-speed oscillation clock
1 Operates with high-speed system clock
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
2. Setting XSEL and MCM0 to 1 and 0, respectively, is prohibited in PLL mode.
3. A clock other than f
PRS is supplied to the following peripheral functions regardless of
the setting of XSEL and MCM0.
 Watchdog timer (operates with internal low-speed oscillation clock)
 When “f
TMX” is selected as the count clock for 16-bit timers X0 and X1 (operates
with TMX control clock)
 When “f
IL”, “fIL/2
6
”, or “fIL/2
15
” is selected as the count clock for 8-bit timer H1
(operates with internal low-speed oscillation clock)
 Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM00 is selected (TI000 pin valid edge))