Datasheet
78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 162
Feb 28, 2012
Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other
(MCS = 1) than the internal high-speed oscillation clock. Specifically, set under either of
the following conditions.
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
Remarks 1. The source clock supplied to the peripheral hardware differs depending on the SELPLL
setting.
SELPLL 16 bit timer X0, X1 Peripheral hardware
0 fPRS = fXP fPRS = fXP
1 When TXnCKS0 = 0: fTMX = 10 fXP
(40 MHz: fXP = 4 MHz operation)
When TXnCKS0 = 0: f
PRS = 10 fXP1/2
(20 MHz: fXP = 4 MHz operation)
f
PRS = 10 fXP1/2
(20 MHz: f
XP = 4 MHz operation)
2. TXnCKS0: Bit 0 of the 16 bit timer Xn operation control register 0 (TXnCTL0)
(4) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU
operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 80H R/W
Symbol <7> 6 5 4 3 2 1 0
MOC MSTOP 0 0 0 0 0 0 0
Control of high-speed system clock operation
MSTOP
X1 oscillation mode External clock input mode
0 X1 oscillator operating External clock from EXCLK pin is enabled
1 X1 oscillator stopped External clock from EXCLK pin is disabled
Cautions 1. Clear MSTOP to 0 while the regulator mode control register (RMC) is 00H.
2. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other (MCS = 0) than the high-speed system clock.
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
3. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (input port mode).
4. The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the peripheral
hardware clock has been stopped, initialize the peripheral hardware.