Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 161
Feb 28, 2012
Figure 5-4. Format of Internal Oscillation Mode/PLL control Register (RCM)
Address: FFA0H After reset: 80H
Note 1
R/W
Note 2
Symbol <7> 6 <5> <4> <3> 2 <1> <0>
RCM RSTS 0 PLLS PLLON SELPLL 0 LSRSTOP RSTOP
RSTS Status of internal high-speed oscillator
0 Waiting for accuracy stabilization of internal high-speed oscillator
1 Stability operating of internal high-speed oscillator
PLLS Status of PLL clock mode
0 Clock-through mode
1 PLL mode
PLLON Control of PLL operation
Notes 3, 4
0 Stops PLL operation
1 Enables PLL operation
SELPLL PLL clock mode selection
Note 5
0 Clock-through mode
1 PLL mode
LSRSTOP Internal low-speed oscillator oscillating/stopped
0 Internal low-speed oscillator oscillating
1 Internal low-speed oscillator stopped
RSTOP Internal high-speed oscillator oscillating/stopped
0 Internal high-speed oscillator oscillating
1 Internal high-speed oscillator stopped
Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to
80H after internal high-speed oscillator has been stabilized.
2. Bits 7 and 5 are read-only.
3. A 10  s wait occurs as an internal stabilization wait time after PLLON = 1 is set.
4. Only 4 MHz can be used for the PLL reference clock oscillation frequency.
5. The PLL clock mode is actually switched when the following time has elapsed after SELPLL
was set.
 SELPLL 0  1: One clock of the clock before the mode was switched to PLL clock mode
(MAX.)
 SELPLL 1  0: Three clocks of the clock before the mode was switched to PLL clock mode
(MAX.)