Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 159
Feb 28, 2012
Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL)
Address: FF9FH After reset: 00H R/W
Symbol <7> <6> 5 4 3 2 1 0
OSCCTL EXCLK OSCSEL 0 0 0 0 0 0
EXCLK OSCSEL High-speed system clock
pin operation mode
P121/X1 pin P122/X2/EXCLK pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input
mode
Input port External clock input
Cautions 1. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of
the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
2. Be sure to clear bits 0 to 5 to 0.
Remark f
XH: High-speed system clock frequency
(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 01H R/W
Symbol 7 6 5 4 3 2 1 0
PCC 0 0 0 0 0 PCC2 PCC1 PCC0
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2. The peripheral hardware clock (f
PRS) is not divided when the division ratio of the PCC
is set.
Remark f
XP: Main system clock oscillation frequency
PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/2
2
0 1 1 fXP/2
3
1 0 0 fXP/2
4
Other than above Setting prohibited