Datasheet

78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 157
Feb 28, 2012
Figure 5-1. Block Diagram of Clock Generator
LSRSTOP
RSTS RSTOP
CPU
PCC2 PCC1 PCC0
OSTS1 OSTS0OSTS2
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
MCM0
XSEL
MCS
MSTOP
STOP
EXCLK
OSCSEL
3
f
XP
f
XP
2
f
XP
2
2
f
XP
2
3
f
XP
2
4
f
IH
f
XH
f
PRS
f
TMX
f
CPU
16-bit timer X0, X1 (40 MHz)
PLL
(x10)
1/2
SELPLLPLLON
Peripheral
hardware
clock switch
System
clock
switch
Prescaler
Internal bus
PLLS
Controller
Select an oscillation
frequency by option byte
Clock operation mode
select register
(OSCCTL)
Main OSC
control register
(MOC)
Main clock mode register (MCM)
Processor clock control register (PCC)
Oscillation stabilization time select register (OSTS)
Main clock mode register (MCM)
Peripheral hardware
Watchdog timer, 8-bit timer H1
Internal bus
Oscillation stabilization time counter status register (OSTC)
Option byte 1:
Cannot be stopped
0:
Can be stopped
Internal oscillation mode/ PLL control register (RCM)
X1/P121
X2/EXCLK
/P122
f
IL
f
X
f
EXCLK
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
Internal high-
speed oscillator
(4 MHz (TYP.)/
8 MHz (TYP.))
X1 oscillation
stabilization time counter
Selector
Selector
Internal low-
speed oscillator
(30 kHz (TYP.))
Note
Note Only 4 MHz can be used for the oscillation frequency.