Datasheet
78K0/Ix2 CHAPTER 5 CLOCK GENERATOR
R01UH0010EJ0500 Rev.5.00 156
Feb 28, 2012
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode select register (OSCCTL)
Processor clock control register (PCC)
Internal oscillation mode/PLL control register (RCM)
Main OSC control register (MOC)
Main clock mode register (MCM)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillators Hi-speed system clock oscillator
Internal high-speed oscillator
Internal low-speed oscillator
The register settings specify the clocks to be supplied as the main system clock, peripheral hardware clock, and TMX
control clock as follows.
Table 5-2. Clocks Supplied to Main System Clock, Peripheral Hardware Clock, and TMX Control Clock
XSEL MCM0 SELPLL Main system clock (fXP) Peripheral hardware clock (fPRS) TMX control clock (fTMX)
0 0
1
0 Internal high-speed oscillator clock (fIH)
0 0
1
1 10 times the internal high-speed oscillation clock (fIH) 1/2 10 times the internal high-
speed oscillation clock (f
IH)
1 0 0 Internal high-speed oscillator
clock (f
IH)
High-speed system clock (f
XH)
1 0 1
Setting prohibited
1 1 0 High-speed system clock (fXH)
1 1 1 10 times the high-speed system clock (fXH) 1/2 10 times the high-speed
system clock (f
XH)
Remark XSEL: Bit 2 of the main clock mode register (MCM)
MCM0: Bit 0 of MCM
SELPLL: Bit 3 of the internal oscillation mode/PLL control register (RCM)