Datasheet
78K0/Ix2 CHAPTER 4 PORT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 153
Feb 28, 2012
Table 4-16. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/IB2 (32 pins)) (2/2)
Alternate Function Pin Name
Function Name I/O
PM P
TOX00 Output 0 0
INTP2 Input 1
P31
TOOLC1 Input
TOX01 Output 0 0
INTP3 Input 1
P32
TOOLD1 I/O
P33 TOX10 Output 0 0
TOX11 Output 0 0
INTP4 Input 1
<TOH1> Output 0 0
P34
<TI51> Input 1
Input 1
P35 SCK11
Output 0 1
P36 SI11 Input 1
P37 SO11 Output 0 0
SCLA0
Notes 1, 2
I/O 0 1 P60
TxD6
Note 3
Output 0 1
SDAA0
Notes 1, 2
I/O 0 1 P61
RxD6 Input 1
P70 ANI8
Note 4
Input 1
X1
Note 5
TOOLC0 Input
<TI000> Input
P121
<INTP0> Input
X2
Note 5
EXCLK
Note 5
Input
P122
TOOLD0 I/O
P125 RESET
Note 6
Input
Notes 1. During I
2
C communication, set SCLA0 and SDAA0 to N-ch open drain output (VDD tolerance) mode by using
POM6 register (refer to 4.3 (5) Port output mode register 6 (POM6)).
2. When using an input compliant with the SMBus Specifications in I
2
C communication, select the SMBus input
buffer by using PIM6 register (refer to 4.3 (4) Port input mode register 6 (PIM6)).
3. During UART/DALI communication, set TxD6 to normal output (CMOS output) mode by using POM6 register
(refer to 4.3 (5) Port output mode register 6 (POM6)).
4. The pin function can be selected by using ADPC1 register, PM7 register, and ADS register. Refer to Table
4-12 of 4.2.5 Port 7.
5. When using the P121 and P122 pins to connect a resonator for the main system clock (X1, X2) or to input an
external clock for the main system clock (EXCLK), the X1 oscillation mode or external clock input mode must
be set by using OSCCTL register (for details, refer to 5.3 (1) Clock operation mode select register
(OSCCTL)). The reset value of OSCCTL is 00H (both P121 and P122 are input port pins).
6. Clear RSTM bit (bit 5 of RSTMASK register) to 0 when using P125 as an external reset input (RESET).
Remark : Don’t care
PM: Port mode register
P: Port output latch