Datasheet

78K0/Ix2 CHAPTER 4 PORT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 149
Feb 28, 2012
Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/IA2) (2/2)
Alternate Function Pin Name
Function Name I/O
PM P
SCLA0
Notes 1, 2
I/O 0 1 P60
TxD6
Note 3
Output 0 1
SDAA0
Notes 1, 2
I/O 0 1 P61
RxD6 Input 1

X1
Note 4
  
TOOLC0 Input
 
<TI000> Input
 
P121
<INTP0> Input
 
X2
Note 4
  
EXCLK
Note 4
Input
 
P122
TOOLD0 I/O
 
P125 RESET
Note 5
Input
 
Notes 1. During I
2
C communication, set SCLA0 and SDAA0 to N-ch open drain output (VDD tolerance) mode by using
POM6 register (refer to 4.3 (5) Port output mode register 6 (POM6)).
2. When using an input compliant with the SMBus Specifications in I
2
C communication, select the SMBus input
buffer by using PIM6 register (refer to 4.3 (4) Port input mode register 6 (PIM6)).
3. During UART/DALI communication, set TxD6 to normal output (CMOS output) mode by using POM6 register
(refer to 4.3 (5) Port output mode register 6 (POM6)).
4. When using the P121 and P122 pins to connect a resonator for the main system clock (X1, X2) or to input an
external clock for the main system clock (EXCLK), the X1 oscillation mode or external clock input mode must be
set by using OSCCTL register (for details, refer to 5.3 (1) Clock operation mode select register (OSCCTL)).
The reset value of OSCCTL is 00H (both P121 and P122 are input port pins).
5. Clear RSTM bit (bit 5 of RSTMASK register) to 0 when using P125 as an external reset input (RESET).
Remarks 1. : Don’t care
PM: Port mode register
P: Port output latch
2. Functions in angle brackets < > can be assigned by setting MUXSEL register.