Datasheet

78K0/Ix2 CHAPTER 4 PORT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 136
Feb 28, 2012
(2) Port registers (Pxx)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-28. Format of Port Register (78K0/IY2)
7Symbol 6 5 4 3 2 1 0 Address After reset R/W
R/W
0
P2
0 P25
Note 1
P24
Note 1
P23
Note 1
0 P21
Note 1
P20
Note 1
FF02H 00H (output latch)
0
P3
0 0 P34 P33 P32 P31 0
FF03H 00H (output latch) R/W
0
P12
0 P125 0 0 0 FF0CH 00H R P122
Note 2
P121
Note 2
m = 2, 3, 12; n = 0 to 5
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. If this pin is set as an analog input and to input mode, do not access the output latch.
2. “0” is always read from the output latch of the pin in the X1 oscillation mode or external clock input
mode.
Figure 4-29. Format of Port Register (78K0/IA2)
7
0
Symbol
P0
6
0
5
0
4
0
3
0
2
0
1
0
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
R/W
0
P2
0 P25
Note 1
P24
Note 1
P23
Note 1
P22
Note 1
P21
Note 1
P20
Note 1
FF02H 00H (output latch)
0
P3
0 0 P34 P33 P32 P31 0
FF03H 00H (output latch) R/W
0
P6
0 0 0 0 0 P61 P60
FF06H 00H (output latch) R/W
0
P12
0 P125 0 0 0 FF0CH 00H R P122
Note 2
P121
Note 2
m = 0, 2, 3, 6, 12; n = 0 to 5
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. If this pin is set as an analog input and to input mode, do not access the output latch.
2. “0” is always read from the output latch of the pin in the X1 oscillation mode or external clock input
mode.