Datasheet

78K0/Ix2 CHAPTER 4 PORT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 126
Feb 28, 2012
4.2.4 Port 6
78K0/IY2 78K0/IA2 78K0/IB2
16 Pins 20 Pins 30 Pins/32 Pins

P60/SCLA0/TxD6 P60/SCLA0/TxD6

P61/SDAA0/RxD6 P61/SDAA0/RxD6
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6). When the P60 and P61 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 6 (PU6).
Input to the P60 and P61 pins can be specified through a normal input buffer or an SMBus input buffer in 1-bit units,
using port input mode register 6 (PIM6).
Output from the P60 and P61 pins can be specified as normal CMOS output or N-ch open-drain output (V
DD tolerance)
in 1-bit units, using port output mode register 6 (POM6).
This port can also be used for serial interface data I/O, and clock I/O.
Reset signal generation sets port 6 to input mode.
Caution To use P60/SCLA0/TxD6 of 78K0/IA2 and 78K0/IB2 as general-purpose port, clear bit 0 (TXDLV6) of
asynchronous serial interface control register 6 (ASICL6) to 0 (normal output of TxD6).
Figures 4-20 and 4-21 show block diagrams of port 6.