Datasheet

78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 95
Feb 28, 2012
3.4.8 Based indexed addressing
[Func
tion]
The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the
HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to
address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits.
A carry from the 16th bit is ignored.
This addressing can be carried out for all of the memory spaces.
[Operand format]
Identifier Description

[HL + B], [HL + C]
[Description example]
MOV A, [HL +B]; when selecting B register
Operation code 10101011
[Illustration]
16 0
H
78
L
07
B
+
07
7 0
A
HL
The contents of the memory
addressed are transferred.
Memory