Datasheet

78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 91
Feb 28, 2012
3.4.4 Short direct addressing
[Func
tion]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function
registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that
are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this
area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is
set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
LB1 EQU 0FE30H ; Defines FE30H by LB1.
:
MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to that
address
Operation code 1 1110010 OP code
0 0110000 30H (saddr-offset)
[Illustration]
15
0
Short direct memory
Effective address
1
111111
87
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH,
 = 0
When 8-bit immediate data is 00H to 1FH,
 = 1