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User’s Manual

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

78K0/Ix2

User’s Manual: Hardware

Rev.5.00 Feb 2012

8-Bit Single-Chip Microcontrollers

www.renesas.com

Summary of content (758 pages)

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User’s Manual 8 78K0/Ix2 User’s Manual: Hardware 8-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.5.
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NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
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How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/Ix2 microcontrollers and design and develop application systems and programs for these devices. The target products are as follows.
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Conventions Data significance: Higher digits on the left and lower digits on the right  (overscore over pin and signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information ... or B Numerical representations: Binary ... Decimal Hexadecimal ...H Active low representations: Note: Caution: Remark: Related Documents The related documents indicated in this publication may include preliminary versions.
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Documents Related to Development Tools (Software) Document Name RA78K0 Ver.3.80 Assembler Package User’s Manual Note 1 Document No. Operation U17199E Language U17198E Structured Assembly Language U17197E 78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document) CC78K0 Ver.3.70 C Compiler User’s Manual Note 2 Operation SM+ System Simulator User’s Manual ZUD-CD-07-0181-E U17201E Language 78K0 C Compiler CC78K0 Ver. 4.
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CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features........................................................................................................................................... 1 1.2 Ordering Information...................................................................................................................... 3 1.3 Pin Configuration (Top View) .......................
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3.3.4 Register addressing ........................................................................................................................ 88 3.4 Operand Address Addressing .................................................................................................... 88 3.4.1 Implied addressing .......................................................................................................................... 88 3.4.2 Register addressing .................................................
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CHAPTER 6 16-BIT TIMERS X0 AND X1 ......................................................................................... 186 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Functions of 16-Bit Timers X0 and X1...................................................................................... 186 Configuration of 16-Bit Timers X0 and X1 .............................................................................. 187 Registers Controlling 16-Bit Timers X0 and X1...........................................................
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CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 357 10.1 10.2 10.3 10.4 Functions of Watchdog Timer................................................................................................. 357 Configuration of Watchdog Timer .......................................................................................... 358 Register Controlling Watchdog Timer....................................................................
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14.4.4 Dedicated baud rate generator.................................................................................................... 467 14.4.5 Calculation of baud rate .............................................................................................................. 469 CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 474 15.1 15.2 15.3 15.4 Functions of Serial Interface IICA.......................................
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18.4.1 Maskable interrupt acknowledgment ........................................................................................... 593 18.4.2 Software interrupt request acknowledgment ............................................................................... 595 18.4.3 Multiple interrupt servicing........................................................................................................... 596 18.4.4 Interrupt request hold .................................................................
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25.4.3 Port pins ...................................................................................................................................... 656 25.4.4 REGC pin .................................................................................................................................... 656 25.4.5 Other signal pins ......................................................................................................................... 656 25.4.6 Power supply.................................
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28.5.5 Comparator ................................................................................................................................. 709 28.5.6 POC ............................................................................................................................................ 711 28.5.7 Supply Voltage Rise Time ........................................................................................................... 712 28.5.8 LVI..................................................
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R01UH0010EJ0500 Rev.5.00 Feb 28, 2012 78K0/Ix2 RENESAS MCU CHAPTER 1 OUTLINE 1.
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78K0/Ix2 CHAPTER 1 OUTLINE  Serial interface  UART6 … Asynchronous 2-wire serial interface  DALI … 2-wire serial interface for lighting control (slave)  IICA … Clock synchronous 2-wire serial interface, multimaster supported standby can be released upon address match in slave mode  CSI11 … Clock synchronous 3-wire serial interface, operable as SPI in slave mode Item UART6/DALI IICA CSI11 – – – Products 78K0/IY2 (16 pins) 78K0/IA2 (20 pins) 1 ch 1 ch 78K0/IB2 (30 pins) 1 ch 78K0/IB2 (
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78K0/Ix2 CHAPTER 1 OUTLINE 1.2 Ordering Information [Part Number] PD78F07xy ΔΔ - xxx -AX Semiconductor -AX Lead- Product contains no lead in any area (Terminal free finish is Ni/Pd/Au plating) xy ΔΔ - xxx Package Type 40, 41, 42 MA-FAA 16-pin plastic SSOP (5.72 mm (225)) 43, 44, 53, MC-CAA 20-pin plastic SSOP (7.62 mm (300)) 54 (IA2) MC-GAB 20-pin plastic SOP (7.62 mm (300)) 45, 46, 55, MC-CAB 30-pin plastic SSOP (7.
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78K0/Ix2 CHAPTER 1 OUTLINE [List of Part Number] 78K0/Ix2 Package Part Number Microcontrollers 78K0/IY2 78K0/IA2 78K0/IB2 16-pin plastic SSOP PD78F0740MA-FAA-AX, 78F0741MA-FAA-AX, 78F0742MA-FAA-AX, (5.72 mm (225)) 78F0750MA-FAA-AX, 78F0751MA-FAA-AX, 78F0752MA-FAA-AX 20-pin plastic SSOP PD78F0743MC-CAA-AX, 78F0744MC-CAA-AX, 78F0753MC-CAA-AX, (7.62 mm (300)) 78F0754MC-CAA-AX 20-pin plastic SOP PD78F0743MC-GAB-AX, 78F0744MC-GAB-AX, 78F0753MC-GAB-AX, (7.
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78K0/Ix2 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 78K0/IY2  16-pin plastic SSOP (5.
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78K0/Ix2 CHAPTER 1 OUTLINE 1.3.2 78K0/IA2  20-pin plastic SSOP (7.62 mm (300))  20-pin plastic SOP (7.
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78K0/Ix2 CHAPTER 1 OUTLINE 1.3.3 78K0/IB2  30-pin plastic SSOP (7.
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78K0/Ix2 CHAPTER 1 OUTLINE AVREF ANI0/P20/AMP-Note ANI1/P21/AMPOUTNote/PGAINNote ANI2/P22/AMP+Note ANI3/P23/CMP2+ P00/TI000/INTP0// P31/TOX00/INTP2/TOOLC1 P32/TOX01/INTP3/TOOLD1  32-pin plastic WQFN (fine pitch) (5 x 5) (1/2) 32 31 30 29 28 27 26 25 AVSS IC0 ANI7/P27 ANI8/P70 IC0 IC0 ANI6/P26/CMPCOM ANI5/P25/CMP1+ 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 P33/TOX10 P34/TOX11/INTP4// P35/SCK11 P36/SI11 P37/SO11 VDD IC0 VSS ANI4/P24/CMP0+ P60/SCLA0/TxD6 P61/SDAA0/RxD6 P02/SSI11/
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78K0/Ix2 CHAPTER 1 OUTLINE  32-pin plastic WQFN (fine pitch) (5 x 5) (2/2) Note AMP- , AMP+ Note : Amplifier Input REGC : Regulator Capacitance Amplifier Output RESET : Reset Programmable Gain RxD6 : Receive Data Amplifier Input SCLA0, SCK11 : Serial Clock Input/Output ANI0 to ANI8 : Analog Input SDAA0 : Serial Data Input/Output AVREF : Analog Reference SI11 : Serial Data Input AMPOUT Note Note PGAIN : : Voltage SO11 : Serial Data Output AVSS : Analog Ground SSI11 : S
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78K0/Ix2 CHAPTER 1 OUTLINE 1.4 Block Diagram 1.4.
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78K0/Ix2 CHAPTER 1 OUTLINE 1.4.
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78K0/Ix2 CHAPTER 1 OUTLINE 1.4.
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78K0/Ix2 CHAPTER 1 OUTLINE  32-pin TOX00/P31 TOX01/P32 16-bit TIMER X0 TOX10/P33 TOX11/P34 16-bit TIMER X1 /P121 TI000/P00 RxD6/P61 (LINSEL) 16-bit TIMER/ EVENT COUNTER 00 /P00 8-bit TIMER/ EVENT COUNTER 51 /P34 /P00 78K/0 CPU CORE 2 P00, P02 PORT 2 8 P20 to P27 PORT 3 7 P31 to P37 PORT 6 2 P60, P61 P70 PORT 7 FLASH MEMORY PORT 12 8-bit TIMER H1 /P34 PORT 0 3 P121, P122, P125 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER TxD6/P60 SERIAL INTERF
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78K0/Ix2 CHAPTER 1 OUTLINE 1.5 Outline of Functions (1/2) Item Internal Flash memory memory (self-programming supported) High-Speed RAM Clock Main Memory space 78K0/IY2 78K0/IA2 16 pins 20 pins 4 KB to 16 KB 8 KB and 16 KB 384 bytes to 768 bytes 512 bytes and 768 bytes 78K0/IB2 30 pins 32 pins 64 KB High-speed system (crystal/ceramic oscillation, external clock input) 1 to 10 MHz: VDD = 2.7 to 5.
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78K0/Ix2 CHAPTER 1 OUTLINE (2/2) Item Serial interface 78K0/IY2 78K0/IA2 16 pins 20 pins UART6/DALI – 1 ch IICA – 1 ch CSI11 – 78K0/IB2 30 pins 32 pins 1 ch 10-bit A/D converter 5 ch 6 ch Operational amplifier (Products with operational amplifier) 1 ch (only PGA mode) 1 ch (single amplifier mode and PGA mode) Comparator 3 ch Multiplier 8 bits  8 bits = 16 bits, 16 bits  16 bits = 32 bits Vectored interrupt External Internal sources Internal 7 7 9 8 8 12 13 13 Reset •
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins Note AVREF P20 to P27, P70 VDD Pins other than P20 to P27, P70 Note Note 78K0/IY2: P20, P21, P23 to P25 78K0/IA2: P20 to P25 78K0/IB2: P20 to P27, P70 R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.1.1 78K0/IY2 (1) Port functions: 78K0/IY2 Function Name I/O Port 2. I/O P20 Function After Reset Analog input 5-bit I/O port. P21 ANI0 ANI1/PGAIN Input/output can be specified in 1-bit units. P23 Alternate Function Note ANI3/CMP2+ P24 ANI4/CMP0+ P25 ANI5/CMP1+ P31 Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IY2 (2/2) Function Name INTP0 I/O Input Function External interrupt request input for which the valid edge After Reset Input port Alternate Function P121/X1/TOOLC0/ (rising edge, falling edge, or both rising and falling TI000 edges) can be specified P125/RESET/TI000 INTP2 P31/TOX00/TOOLC1 INTP3 P32/TOX01/TOOLD1 INTP4 P34/TOX11/TOH1/ TI51  REGC RESET Input Connecting regulator output (2.0 V/2.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.1.2 78K0/IA2 (1) Port functions: 78K0/IA2 Function Name P00 I/O I/O Function Port 0. After Reset Input port Alternate Function TI000/INTP0/TOH1/ TI51 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 6-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IA2 (1/2) Function Name ANI0 I/O Input Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP- Note Note P21/AMPOUT ANI1 / Note PGAIN Note ANI2 P22/AMP+ ANI3 P23/CMP2+ ANI4 P24/CMP0+ ANI5 P25/CMP1+ Note AMP- AMP+ Input Operational amplifier input Analog input Note AMPOUT P20/ANI0 P22/ANI2 Note CMP0+ Output Operational amplifier output Analog input P21/ANI1/PGAIN Input Comparat
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IA2 (2/2) Function Name TI000 TI51 I/O Input Input Function After Reset External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Input port External count clock input to 8-bit timer/event counter 51 Input port Alternate Function P00/INTP0/TOH1/ TI51 P121/X1/TOOLC0/ INTP0 P00/TI000/INTP0/ TOH1 P34/TOX11/INTP4/ TOH1 TOH1 Output 8-
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.1.3 78K0/IB2 (30 pins) (1) Port functions: 78K0/IB2 (30 pins) Function Name P00 I/O I/O Function Port 0. P01 3-bit I/O port. P02 Use of an on-chip pull-up resistor can be specified by a After Reset Input port Alternate Function TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. SSI11/INTP5 software setting. P20 I/O Port 2. Analog input 8-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IB2 (30 pins) (1/2) Function Name ANI0 I/O Input Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP- Note Note P21/AMPOUT ANI1 / Note PGAIN Note ANI2 P22/AMP+ ANI3 P23/CMP2+ ANI4 P24/CMP0+ ANI5 P25/CMP1+ ANI6 P26/CMPCOM ANI7 P27 ANI8 P70 Note AMP- AMP+ Input Operational amplifier input Analog input Note AMPOUT P20/ANI0 P22/ANI2 Note CMP0+ Output Operational amplifier out
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IB2 (30 pins) (2/2) Function Name I/O Function After Reset Alternate Function SCK11 I/O Clock input/output for CSI11 SI11 Input Serial data input to CSI11 P36 SO11 Output Serial data output from CSI11 P37 SSI11 Input Chip select input to CSI11 Input port P02/INTP5 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.1.4 78K0/IB2 (32 pins) (1) Port functions: 78K0/IB2 (32 pins) Function Name P00 I/O I/O P02 Function Port 0. After Reset Input port Alternate Function TI000/INTP0/TOH1/ 2-bit I/O port. TI51 Input/output can be specified in 1-bit units. SSI11/INTP5 Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 8-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IB2 (32 pins) (1/2) Function Name ANI0 I/O Input Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP- Note Note P21/AMPOUT ANI1 / Note PGAIN Note ANI2 P22/AMP+ ANI3 P23/CMP2+ ANI4 P24/CMP0+ ANI5 P25/CMP1+ ANI6 P26/CMPCOM ANI7 P27 ANI8 P70 Note AMP- AMP+ Input Operational amplifier input Analog input Note AMPOUT P20/ANI0 P22/ANI2 Note CMP0+ Output Operational amplifier out
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/IB2 (32 pins) (2/2) Function Name I/O Function After Reset Alternate Function SCK11 I/O Clock input/output for CSI11 SI11 Input Serial data input to CSI11 P36 SO11 Output Serial data output from CSI11 P37 SSI11 Input Chip select input to CSI11 Input port P02/INTP5 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P00 to P02 (port 0) P00 to P02 function as an I/O port. These pins also function as timer I/O, external interrupt request input, and chip select input.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (g) SSI11 This is a chip select input pin of serial interface CSI11. 2.2.2 P20 to P27 (port 2) P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input, operational amplifier I/O, and PGA input.
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78K0/Ix2 (f) CHAPTER 2 PIN FUNCTIONS CMPCOM This is a comparator common input pin. Caution ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 2.2.3 P30 to P37 (port 3) P30 to P37 function as an I/O port. These pins also function as pins for external interrupt request input, timer I/O, clock input and data I/O for flash memory programmer/on-chip debugger, and clock input and data I/O for serial interface.
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78K0/Ix2 (f) CHAPTER 2 PIN FUNCTIONS TOOLC1 This is a clock input pin for flash memory programmer/on-chip debugger. (g) TOOLD1 This is a data I/O pin for flash memory programmer/on-chip debugger. (h) SCK11 This is a serial clock I/O pin of serial interface CSI11. (i) SI11 This is a serial data input pin of serial interface CSI11. (j) SO11 This is a serial data output pin of serial interface CSI11.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (c) RxD6 This is a serial data input pin for serial interface UART6. (d) TxD6 This is a serial data output pin for serial interface UART6. 2.2.5 P70 (port 7) P70 functions as an I/O port. This pin also functions as pin for A/D converter analog input. 78K0/IY2 78K0/IA2 78K0/IB2 16 Pins 20 Pins 30 Pins/32 Pins   P70/ANI8 The following operation modes can be specified in 1-bit units. (1) Port mode P70 functions as an I/O port.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (1) Port mode P121, P122, and P125 function as an input port. Only for P125, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P121, P122, and P125 function as pins for external interrupt request input, connecting resonator for main system clock, external clock input for main system clock, external reset input, timer input, and clock input and data I/O for flash memory programmer/on-chip debugger.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS (a) AVREF This is the A/D converter reference voltage input pin, and the positive power supply pin of A/D converter and ports 2 and 7. Note When the A/D converter is not used, connect this pin directly to VDD . Note Make the AVREF pin the same potential as the VDD pin when ports 2 and 7 are used as the digital ports. (b) AVSS This is a ground potential pin of A/D converter and ports 2 and 7.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Tables 2-2 to 2-5 show the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (78K0/IY2) Pin Name I/O Circuit Type ANI0/P20 Note 1 Independently connect to AVREF or VSS via a resistor.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (78K0/IA2) Pin Name I/O Circuit Type P00/TI000/INTP0/TOH1/ 5-AQ I/O Recommended Connection of Unused Pins Input: I/O TI51 Independently connect to VDD or VSS via a resistor. Output: Leave open. Note 1 ANI0/P20/AMP- 11-P Note 1 ANI1/P21/AMPOUT Independently connect to AVREF or VSS via a resistor.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Table 2-4. Pin I/O Circuit Types (78K0/IB2 (30 Pins)) Pin Name I/O Circuit Type P00/TI000/INTP0 I/O I/O 5-AQ Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P01/TO00/TI010 P02/SSI11/INTP5 Note 1 ANI0/P20/AMP- Note 1 ANI1/P21/AMPOUT / 11-P 11-O Independently connect to AVREF or AVSS via a resistor.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Table 2-5. Pin I/O Circuit Types (78K0/IB2 (32 Pins)) Pin Name I/O Circuit Type P00/TI000/INTP0/TOH1/ 5-AQ I/O Recommended Connection of Unused Pins Input: I/O TI51 Independently connect to VDD or VSS via a resistor. Output: Leave open. P02/SSI11/INTP5 Note 1 ANI0/P20/AMP- Note 1 ANI1/P21/AMPOUT / 11-P 11-O Independently connect to AVREF or AVSS via a resistor.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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78K0/Ix2 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (3/3) Type 37-A Type 42-A VDD X2 pullup enable input enable P-ch N-ch IN input enable X1 input enable R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/Ix2 microcontrollers can access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding to each product as indicated below after release of reset. Table 3-1.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-1.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-3.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-4.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, refer to CHAPTER 24 OPTION BYTE.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/Ix2 microcontrollers, based on operability and other considerations.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-5.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-6.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/Ix2 microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (refer to 18.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE).
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP SP R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP SP R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-6.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Address Symbol 7 FF60H FF61H Note AMP0M  FF62H C0CTL FF63H C0RVM FF64H C1CTL FF65H C1RVM FF66H C2CTL FF67H C2RVM FF68H FF69H  CMPFLG FF6AH  FF6BH  FF6CH TMHMD1 FF6DH TMCYC1 FF6EH HIZTREN FF6FH HIZTRS FF70H 0  6  S1> S0> 0 0 S1> S0> 0 0 0 S1> S0> 0 0 0   0
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Address FF79H to FF7DH Symbol  7 6 5 4 3 2 1 0         0 0 0 0 0 MCINV> WM> 0 0 0 SET0> TX0CTL4 0 0 FF83H TX0IOC0 0 0 0 FF85H FF86H FF87H TX0CR0 TX0CR1 CKS2> CKS1> CKS0> 0 0 0 0 CS> P1RP> Manipulated After Simultaneo
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Address Symbol 7 6 5 0 0 0 4 R/W 3 2 P> R/W    R/W    00H 177 R/W    80H 176 R    00H 178, 606 R/W    05H 179, 607     FFA4H FFB7H 00H 
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 FF00H P0  FF01H FF02H P2 FF03H P3 FF04H FF05H RXBDL 6 5 4 3 2 1 0 1 8 page Address Reference Table 3-7.
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K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously  FF24H  FF25H FF26H PM6 7 6 5 4 3 2 1 0         1 8 16      page Address Reference Table 3-7.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-7.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-7.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 page Address Reference Table 3-7.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF00H P0  FF01H 7 6 5 4 3 2 1 0 0 0 0 0 0 P02 P01 P00        page Address Reference Table 3-8.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-8.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-8.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-8.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF00H P0  FF01H 7 6 5 4 3 2 1 0 0 0 0 0 0 P02 0 P00        page Address Reference Table 3-9.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-9.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-9.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-9.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 0 X 15 8 7 0 PC 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored.
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78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 4-1.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (78K0/IY2) Function Name P20 I/O I/O Function Port 2. After Reset Analog input 5-bit I/O port. P21 ANI0 ANI1/PGAIN Input/output can be specified in 1-bit units. P23 Alternate Function Note ANI3/CMP2+ P24 ANI4/CMP0+ P25 ANI5/CMP1+ P31 I/O P32 P33 P34 Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Functions (78K0/IA2) Function Name P00 I/O I/O Function Port 0. After Reset Input port Alternate Function TI000/INTP0/TOH1/ TI51 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 6-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-4. Port Functions (78K0/IB2 (30 Pins)) Function Name P00 I/O I/O Function Port 0. After Reset Input port 3-bit I/O port. P01 TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. P02 Alternate Function SSI11/INTP5 Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 8-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-5. Port Functions (78K0/IB2 (32 Pins)) Function Name P00 I/O I/O P02 Function Port 0. After Reset Input port Alternate Function TI000/INTP0/TOH1/ 3-bit I/O port. TI51 Input/output can be specified in 1-bit units. SSI11/INTP5 Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 8-bit I/O port. P21 ANI0/AMP- Note ANI1/AMPOUT Input/output can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-6.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 78K0/IY2 78K0/IA2 78K0/IB2 16 Pins 20 Pins  P00/TI000/INTP0/TOH1/TI51 P00/TI000/INTP0 P00/TI000/INTP0/TOH1/TI51   P01/TO00/TI010    P02/SSI11/INTP5 30 Pins 32 Pins P02/SSI11/INTP5 Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL). Port 0 is an I/O port with an output latch.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-1. Block Diagram of P00 (2/2) (2) 78K0/IB2 (30 Pins) VDD WRPU PU0 PU00 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00) P00/TI000/INTP0 WRPM PM0 PM00 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 VDD WRPU PU0 PU01 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P01) P01/TI010/TO00 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 VDD WRPU PU0 PU02 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P02) P02/SSI11/INTP5 WRPM PM0 PM02 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-8. Setting Functions of P21/ANI1/AMPOUT/PGAIN Pin ADPC0 PM2 Register Register Digital OPAMP0E Note bit Input mode PGAEN  0 I/O selection 1  Output mode 0  Input mode 0 0 selection 0 P21/ANI1/AMPOUT/PGAIN Pin Selects ANI1. Setting prohibited Does not select ANI1. Digital input  Setting prohibited Selects ANI1. Setting prohibited Does not select ANI1.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-9. Setting Functions of P23/ANI3/CMP2+, P24/ANI4/CMP0+, P25/ANI5/CMP1+ Pins ADPC0 PM2 Register CMPmEN bit ADS Register P23/ANI3/CMP2+, P24/ANI4/CMP0+, (m = 0 to 2) (n = 3 to 5) P25/ANI5/CMP1+ Pins Register Digital I/O  Input mode Selects ANIn. Setting prohibited Does not select ANIn. Digital input Selects ANIn. Setting prohibited Does not select ANIn. Digital output 0 Selects ANIn.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-11. Setting Functions of P27/ANI7 Pin ADPC0 Register Digital I/O selection PM2 Register Input mode Output mode Analog input Input mode selection ADS Register Selects ANI7. Setting prohibited Does not select ANI7. Digital input Selects ANI7. Setting prohibited Does not select ANI7. Digital output Selects ANI7. Analog input (to be converted into digital signal) Does not select ANI7.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P20 (1) 78K0/IY2 Internal bus Selector RD WRPORT P2 Output latch (P20) P20/ANI0 WRPM PM2 PM20 A/D converter (2) 78K0/IA2, 78K0/IB2 Internal bus Selector RD WRPORT P2 Output latch (P20) P20/ANI0/AMP-Note WRPM PM2 PM20 A/D converter Operational amplifier (-) inputNote Note Products with operational amplifier only P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 Internal bus Selector RD WRPORT P2 Output latch (P22) P22/ANI2/AMP+Note WRPM PM2 PM22 A/D converter Operational amplifier (+) input Note Products with operational amplifier only Figure 4-7.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P24 Selector Internal bus RD WRPORT P2 Output latch (P24) P24/ANI4/CMP0+ WRPM PM2 PM24 A/D converter Comparator 0 (+) input Figure 4-9. Block Diagram of P25 Selector Internal bus RD WRPORT P2 Output latch (P25) P25/ANI5/CMP1+ WRPM PM2 PM25 A/D converter Comparator 1 (+) input P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P26 Selector Internal bus RD WRPORT P2 Output latch (P26) P26/ANI6/CMPCOM WRPM PM2 PM26 A/D converter Comparator common (-) input Figure 4-11. Block Diagram of P27 Selector Internal bus RD WRPORT P2 Output latch (P27) P27/ANI7 WRPM PM2 PM27 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P30 VDD WRPU PU3 PU30 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P30) P30/TOH1/TI51/INTP1 WRPM PM3 PM30 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P31 VDD WRPU PU3 PU31 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P31) P31/TOX00/INTP2/TOOLC1 WRPM PM3 PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P32 VDD WRPU PU3 PU32 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P32) P32/TOX01/INTP3/TOOLD1 WRPM PM3 PM32 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P33 VDD WRPU PU3 PU33 P-ch Selector Internal bus RD WRPORT P3 Output latch (P33) P33/TOX10 WRPM PM3 PM33 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-16 Block Diagram of P34 (1/2) (1) 78K0/IY2, 78K0/IA2, 78K0/IB2 (32 Pins) VDD WRPU PU3 PU34 P-ch Alternate function (INTP4) TM5SEL1Note RD Input signal from P00/TI51Note Selector Alternate function (TI51) TM5SEL0 Selector Internal bus MUXSEL WRPORT P3 Output latch (P34) P34/TOX11/INTP4// Selector Alternate function (TOX11) Alternate function (TOH1) WRPM PM3 Output signal to P00/TOH1Note TMHSEL1Note TMHSEL0 MUXSEL PM34 P3: Port regis
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-16 Block Diagram of P34 (2/2) (2) 78K0/IB2 (30 Pins) VDD WRPU PU3 PU34 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P34) P34/TOX11/INTP4 WRPM PM3 PM34 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P35 VDD WRPU PU3 PU35 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P35) P35/SCK11 WRPM PM3 PM35 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P36 VDD WRPU PU3 PU36 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P36) P36/SI11 WRPM PM3 PM36 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P37 VDD WRPU PU3 PU37 P-ch Selector Internal bus RD WRPORT P3 Output latch (P37) P37/SO11 WRPM PM3 PM37 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 6 78K0/IY2 78K0/IA2 78K0/IB2 16 Pins 20 Pins 30 Pins/32 Pins  P60/SCLA0/TxD6 P60/SCLA0/TxD6  P61/SDAA0/RxD6 P61/SDAA0/RxD6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P60 and P61 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P60 VDD WRPU PU6 PU60 P-ch PIM6 Alternate function PIM60 Selector Internal bus RD WRPORT P6 Output latch (P60) POM6 POM60 P60/SCLA0/TxD6 WRPM PM6 PM60 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PIM6: Port input mode register 6 POM6: Port output mode register 6 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P61 VDD WRPU PU6 PU61 P-ch PIM6 Alternate function PIM61 Selector Internal bus RD WRPORT P6 Output latch (P61) POM6 POM61 P61/SDAA0/RxD6 WRPM PM6 PM61 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PIM6: Port input mode register 6 POM6: Port output mode register 6 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
PAGE 142
78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 7 78K0/IY2 78K0/IA2 78K0/IB2 16 Pins 20 Pins 30 Pins/32 Pins   P70/ANI8 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). This port can also be used for A/D converter analog input. When using P70/AM8, set the registers according to the pin function to be used (refer to Table 4-12). Table 4-12.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P70 Selector Internal bus RD WRPORT P7 Output latch (P70) P70/ANI8 WRPM PM7 PM70 A/D converter P7: Port register 7 PM7: Port mode register 7 RD: Read signal WR: Write signal R01UH0010EJ0500 Rev.5.
PAGE 144
78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 12 78K0/IY2 78K0/IA2 78K0/IB2 16 Pins 20 Pins 30 Pins/32 Pins P121/X1/TOOLC0// P121/X1/TOOLC0// P121/X1/TOOLC0// P122/X2/EXCLK/TOOLD0 P122/X2/EXCLK/TOOLD0 P122/X2/EXCLK/TOOLD0 P125/RESET// P125/RESET P125/RESET Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL). P121, P122, P125 function as an Input port.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P121, P122 OSCCTL OSCSEL RD Internal bus P122/X2/EXCLK/TOOLD0 OSCCTL EXCLK, OSCSEL RD P121/X1/TOOLC0// MUXSEL INTP0SEL1Note INTP0SEL0 TM00SEL1Note TM00SEL0 Alternate function MUXSEL: Port alternate switch control register OSCCTL: Clock operation mode select register RD: Read signal WR: Write signal Note 78K0/IY2 only R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-24.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following eight types of registers.  Port mode registers (PMxx)  Port registers (Pxx)  Pull-up resistor option registers (PUxx)  Port input mode register 6 (PIM6)Note 1  Port output mode register 6 (POM6)Note 1  Reset pin mode register (RSTMASK)  A/D port configuration registers 0, 1Note 2 (ADPC0, ADPC1Note 2)  Port alternate switch control register (MUXSEL) Notes 1.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-26.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-28.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-30.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-32.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Note (4) Port input mode register 6 (PIM6) This register sets the input buffer of P60 and P61 in 1-bit units. When using an input compliant with the SMBus specifications in I2C communication, set PIM60 and PIM61 to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note 78K0/IA2, 78K0/IB2 only Figure 4-34.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Note (5) Port output mode register 6 (POM6) This register sets the output mode of P60 and P61 in 1-bit units. 2 During I C communication, set POM60 and POM61 to 1. When using the P60/TxD6/SCLA0 pin as the data output of serial interface UART6/DALI, clear POM60 to 0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note 78K0/IA2, 78K0/IB2 only Figure 4-35.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-37.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-38. Format of A/D Port Configuration Register 1 (ADPC1) (78K0/IB2 Only) Address: FF2FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC1 0 0 0 0 0 0 0 ADPCS8 ADPCS8 Digital I/O or analog input selection 0 Analog input 1 Digital I/O Cautions 1. Set the pin set to analog input to the input mode by using port mode register 7 (PM7). 2. If data is written to ADPC1, a wait cycle is generated.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Figure 4-39.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Tables 4-13 to 4-16. Table 4-13.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/IY2) (2/2) Pin Name Alternate Function Function Name P121 P122 X1 P   I/O Note 1  TOOLC0 Input   Input   Input   X2 Note 1 EXCLK  Note 1 TOOLD0 P125 PM Note 2   Input   I/O   RESET Input   Input   Input   Notes 1.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-14.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-14.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-15.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-15.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-16.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS Table 4-16.
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78K0/Ix2 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by using the main clock mode register (MCM).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1.
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R01UH0010EJ0500 Rev.5.00 Feb 28, 2012 External input clock Crystal/ceramic oscillation fXH Internal highspeed oscillator (4 MHz (TYP.)/ 8 MHz (TYP.)) Select an oscillation frequency by option byte fEXCLK fX MSTOP fIH STOP Main clock mode register (MCM) MCS Note Only 4 MHz can be used for the oscillation frequency.
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78K0/Ix2 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: Internal high-speed oscillation clock frequency fEXCLK: External main system clock frequency fXH: High-speed system clock frequency fXP: Main system clock frequency fIL: Internal low-speed oscillation clock frequency fCPU: CPU clock frequency fPRS: Peripheral hardware clock frequency fTMX: TMX control clock frequency 5.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Figure 5-2.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Ix2 microcontrollers. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-3. Table 5-3.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Figure 5-4.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other (MCS = 1) than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. Remarks 1. The source clock supplied to the peripheral hardware differs depending on the SELPLL setting.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (5) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-6.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (clock-through mode: 1 to 10 MHz, PLL mode: 4 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal (clock-through mode: 1 to 10 MHz, PLL mode: 4 MHz) to the EXCLK pin. Figure 5-9 shows an example of the external circuit of the X1 oscillator. Figure 5-9.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 X2 B C High current (e) Signals are fetched VSS X1 X2 5.4.2 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/Ix2 microcontrollers.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.4.3 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/Ix2 microcontrollers. The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock. “Can be stopped by software” or “Cannot be stopped” can be selected by the option byte.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Here is an example when using PLL (flow chart). Figure 5-11. Setting Example When Using PLL (Flow Chart) (When Multiplying Internal High-Speed Oscillation Clock) Reset release No RSTS = 1? Waits for the accuracy of the internal high-speed oscillation to stabilize. Yes PLLON←1 : Starts to operate the PLL.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (refer to Figure 5-1).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0)) Power supply voltage (VDD) 2.7 V 1.61 V (TYP.) 0.5 V/ms (MIN.) 0V Internal reset signal <1> <3> Waiting for voltage stabilization (0.93 to 3.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Cautions 1. If the rise of the voltage to reach 2.7 V after turning on the power is more gradual than 0.5 V/ms (MIN.), perform one of the following operations.  Input a low level to the RESET pin until 2.7 V is reached after turning on the power.  Set the LVI default start function to operate (LVISTART = 1) using the option byte and perform a wait processing until the supply voltage rises from 1.91 V (TYP.) to 2.7 V (see Figure 5-13).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal highspeed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (1) Example of setting procedure when oscillating the X1 clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (MCM registers) Confirm with MCS that the CPU is operating on a clock other than the internal hi-speed oscillation clock. When MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to the internal hi-speed oscillation clock.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1>  Restarting oscillation of the internal high-speed oscillation clockNote (Refer to 5.6.2 (1) Example of setting procedure when restarting oscillation of the internal highspeed oscillation clock).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock.  Watchdog timer  8-bit timer H1 (if fIL is selected as the count clock) In addition, the following operation modes can be selected by the option byte.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0)) Power ON Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (input port mode) PLL: Stops VDD < 1.61 V (TYP.) (A) VDD ≥ 1.61 V (TYP.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A)  (B) SFR registers do not have to be set (default status after reset release).
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/3) (4) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 0 Confirm this flag is 1.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR Table 5-4.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the preswitchover clock for several clocks (refer to Table 5-6). Table 5-6.
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78K0/Ix2 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-8.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.1 Functions of 16-Bit Timers X0 and X1 16-bit timers X0 and X1 are mounted onto all 78K0/Ix2 microcontroller products. 16-bit timers X0 and X1 are dedicated PWM output timers and have two outputs each, enabling the generation of up to four PWM outputs. Complementary PWM output can also be generated to control a half-bridge circuit (2 outputs) or fullbridge circuit (4 outputs).
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.2 Configuration of 16-Bit Timers X0 and X1 16-bit timers X0 and X1 include the following hardware. Table 6-1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-3.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (1) 16-bit timer Xn capture/compare register 0 (TXnCCR0) This is a 16-bit register that can switch between being used for the capture function and the compare function. TXnCTL2 is used to switch between the capture function and compare function. This register can be read or written in 16-bit units. Reset signal generation clears this register to 0000H. Figure 6-4.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-5.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (1) 16-bit timer Xn operation control register 0 (TXnCTL0) TXnCTL0 is a register that controls the count operation and sets the count clock of 16-bit timer Xn. TXnCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TXnCTL0 to 00H. Figure 6-6.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-7.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (2) 16-bit timer Xn operation control register 1 (TXnCTL1) TXnCTL1 is a register that sets timer start via detection of INTP0 rising edge, output gate function by TOH1 output, the PWM output operation, and synchronous operation mode. TXnCTL1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TXnCTL1 to 00H. Remark n = 0, 1 Figure 6-8.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Cautions 2. Be sure to clear bits 0 to 2, 6 to 0. 3. When using the output gate function, set bit 0 (TOEN1) of the TMHMD1 register to 1 (enable the TOH1 output). Figure 6-9.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Remarks 1. The capture trigger sources are as follows, according to the operation mode. Operation mode Capture trigger sources TMX0-only start mode INTCMP2, INTP0 TMX1-only start mode INTCMP1 TMX0 and TMX1 Synchronous start 2. TMX0 INTCMP2, INTP0 mode TMX1 INTCMP1 TMX0 and TMX1 Synchronous TMX0 INTCMP2, INTP0 start/clear mode TMX1 INTCMP1 n = 0, 1 Figure 6-10.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-11.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-12.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (5) 16-bit timer Xn operation control register 4 (TXnCTL4) TXnCTL4 is a register that sets the mode of the interlocking function with comparator 0 and comparator 1. TXnCTL4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TXnCTL4 to 00H. Remark n = 0, 1 Figure 6-13.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-14. Format of 16-Bit Timer X1 Operation Control Register 4 (TX1CTL4) Address: FF9AH After reset: 00H R/W Symbol 7 6 5 <4> <3> 2 <1> <0> TX1CTL4 0 0 0 TX1CMP1R TX1CMP1R 0 TX1CMP0R TX1CMP0R M1 M0 M1 M0 TX1CMP1R TX1CMP1R Operation mode of interlocking function via comparator 1 output (interlocking with M1 M0 TMX1 timer) 0 0 Disables operation of interlocking function via comparator 1 output.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (6) 16-bit timer Xn output control register 0 (TXnIOC0) TXnIOC0 is a register that sets the timer output. TXnIOC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TXnIOC0 to 00H. Remark n = 0, 1 Figure 6-15.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-16. 16-bit timer X1 output control register 0 (TX1IOC0) Address: FF9BH After reset: 00H R/W Symbol 7 6 5 4 <3> <2> <1> <0> TX1IOC0 0 0 0 0 TX1TOC1 TX1TOC0 TX1TOL1 TX1TOL0 TX1TOC1 0 TOX11 output control Disables timer output (Fixes to low-level output when TX1TOL1 = 0, and fixes to high-level output when TX1TOL1 = 1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (7) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TOX00/INTP2/TOOLC1, P32/TOX01/INTP3/TOOLD1, P33/TOX10, and P34/TOX11/INTP4 pins for timer output, set PM31 to PM34 and the output latches of P31 to P34 to 0. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM3 to FFH. Figure 6-17.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 The following table shows how the operation modes (TMX0-only mode, TMX1-only mode, TMX0 and TMX1 synchronous start mode, TMX0 and TMX1 synchronous start/clear mode) and register setting bits controlling 16-bit timers X0 and X1 relate to each other. Table 6-2.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Table 6-2.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 The following tables show how the operation modes (TMX0-only mode, TMX1-only mode, TMX0 and TMX1 synchronous start mode, TMX0 and TMX1 synchronous start/clear mode) and the trigger source of each operation (start, capture, interlocking function) relate to each other. Table 6-3.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.4 Operation of 16-Bit Timer/Event Counter 00 (1) Interval timer operation If bit 7 (TXnTMC) of the 16-bit timer Xn operation control register 0 (TXnCTL0) is set to 1, the count operation is started in synchronization with the count clock. When the value of the 16-bit timer counter Xn (TMXn) later matches the value of TXnCRm, TMXn is cleared to 0000H and a match interrupt signal (INTTMXn) is generated.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-19.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-20. Example of Software Processing for Interval Timer Function N N N 16-bit timer counter Xn 0000H Operable bits (TXnTMC) 0 1 TXnCRm register 0 N INTTMXn signal <1> <2> <1> Count operation start flow START Register initial setting TXnCTL1 register, TXnCRm register TXnTMC bit = 1 Initial setting of these registers is performed before setting the TXnTMC bit to 1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (2) A/D conversion start timing signal output If bit 1 (TXnADEN) of the 16-bit timer Xn operation control register 2 (TXnCTL2) is set to 1, the generation of the A/D conversion synchronization trigger is enabled. If bit 7 (TXnTMC) of the 16-bit timer Xn operation control register 0 (TXnCTL0) is set to 1, the count operation is started in synchronization with the count clock.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-22. Example of Register Settings for A/D Conversion Start Timing Signal Output (a) 16-bit timer Xn operation control register 0 (TXnCTL0) TXnTMC 1 TXnCKS2 TXnCKS1 TXnCKS0 0 0 0 0 0/1 0/1 0/1 Selects count clock Starts timer count operation (b) 16-bit timer Xn operation control register 2 (TXnCTL2) TXnADEN TXnCCS 0 0 0 0 0 0 1 0 TXnCCR0 used as compare register. Enable generates A/D conversion synchronization trigger.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-23.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) Capture function If bit 7 (TXnTMC) of the 16-bit timer Xn operation control register 0 (TXnCTL0) is set to 1, the count operation is started in synchronization with the count clock. Then, when the rising edge of the comparator m output or the INTP0 input is detected, the count value of the 16-bit timer counter Xn (TMXn) is captured to a 16-bit timer Xn capture/compare register 0 (TXnCCR0) .
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-25.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-26.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.5 Operation of PWM output operation of 16-Bit Timers X0 and X1 (1) PWM output operation (TMXn-only mode, single output) PWM output is started from TOXn0 if bit 7 (TXnTMC) of TXnCTL0 is set to 1 after setting the count value of the inverted output to TXnCR0 and the count value of the cycle to TXnCR1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-27. Example of Register Settings for PWM Output Operation (Single Mode) (2/2) (b) 16-bit timer Xn operation control register 1  PWM output: TOX00 pin TX0INTPST TX0CTL1 0/1 TX0PWMCE TX0PWMCINV TX0PWM 0 0 0 0 0 0 0 Single output Using the TOX0n output gate function by TOH1 output is prohibited. 0: Starts counting when TX0TMC bit = 1. 1: Starts timer counting when TX0TMC bit = 1 and INTP0 rising edge is detected.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-28.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 To specify PWM output from TOXn0, set TXnCR0 and TXnCR1 to a value in the following range: 0000H  TXnCR0  TXnCR1  TXnCR3 If TXnCR0 = TXnCR1 is specified, the output will be set to the default status (fixed). To specify PWM output from TOXn1, set TXnCR2 and TXnCR3 to a value in the following range: 0000H  TXnCR2  TXnCR3  FFFFH If TXnCR2 = TXnCR3 is specified, the output will be set to the default status (fixed). Notes 1. 2.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-29. Example of Register Settings for PWM Output Operation (Dual Mode) (2/2) (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0 TXnTOL1 TXnTOL0 TXnIOC0 0 0 0 0 1 1 0/1 0/1 0: Normal output (low level) 1: Inverted output (high level) Enables timer output Remark n = 0, 1 Figure 6-30.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) PWM output operation (TMX0 and TMX1 synchronous start mode) Output from the two timer outputs of TMX0 and TMX1 (up to 4 outputs) is simultaneously started. Setting bit 7 (TX0TMC) of TX0CTL1 to 1 starts PWM output. Setting bit 7 (TX0TMC) of TX0CTL1 to 0 stops PWM output. Remark This mode is simultaneously used when starting or stopping output. While the TMX0 and TMX1 are operating, output control is performed according to the setting of each timer.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-31. Example of Register Settings for PWM Output Operation (TMX0 and TMX1 Synchronous Start Mode) (2/2) (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0 TXnTOL1 TXnTOL0 TXnIOC0 0 0 0 0 0/1 0/1 0/1 0/1 0: Normal output (low level) 1: Inverted output (high level) 0: Disables timer output 1: Enables timer output Remark n = 0, 1 R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-32.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (4) PWM output operation (TMX0 and TMX1 synchronous start/clear mode) Output cycles from the two timer outputs of TMX0 and TMX1 (up to 4 outputs) are synchronized. Setting bit 7 (TX0TMC) of TX0CTL1 to 1 starts PWM output. Setting bit 7 (TX0TMC) of TX0CTL1 to 0 stops PWM output. TXnCRm can be rewritten while the timers are operating, and the duty and the pulse cycle can be changed.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (b) TMX0 dual output, TMX1 single output or dual output ● Pulse cycle and duty of TOX00  Pulse cycle = (Set value of TX0CR3 + 1)  Count clock cycle Note 1 Note 1  Duty = (Set value of TX0CR1  Set value of TX0CR0 ) / (Set value of TX0CR3 + 1) ● Pulse cycle and duty of TOX01  Pulse cycle = (Set value of TX0CR3 + 1)  Count clock cycle Note 1 Note 1  Duty = (Set value of TX0CR3  Set value of TX0CR2 ) / (Set value of TX0CR3 + 1) ● Pulse cyc
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-33.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-34.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (5) PWM output operation (PWM output from TOX0n when TOH1 output is at high level) A square wave is output from the TOX0n pin by combining 8-bit timer H1 and 16-bit timer X0, only when the TOH1 output is at high level. See (1) PWM output operation (single output) through (4) PWM output operation (TMX0 and TMX1 synchronous start mode) for the setting of outputting a square wave. Remarks 1. n = 0, 1 2. For the setting of TOH1 output, see CHAPTER 9 8-BIT TIMER H1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-36.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-37. Example of Register Settings for PWM Output Operation (TMX0-Only Operation (Dual Output), PWM Output from TOX00 and TOX01 When TOH1 Output Is at Low Level) (2/2) (b) 16-bit timer X0 operation control register 1 TX0INTPST TX0CTL1 0/1 TX0PWMCE TX0PWMCINV TX0PWM 0 1 1 1 0 0 0 Dual output Performs PWM output from TOXmn pin when TOH1 output is low level. Using the TOX0n output gate function by TOH1 output is enabled.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (7) PWM output operation (PWM output from TOX1n when TOH1 output is at high level) A square wave is output from the TOX1n pin by combining 8-bit timer H1 and 16-bit timer X1, only when the TOH1 output is at high level. See (1) PWM output operation (single output) through (4) PWM output operation (TMX0 and TMX1 synchronous start mode) for the setting of outputting a square wave. Remarks 1. n = 0, 1 2. For the setting of TOH1 output, see CHAPTER 9 8-BIT TIMER H1.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-39. Example of Register Settings for PWM Output Operation (TMX1-Only Operation (Dual Output), PWM Output from TOX10 and TOX11 When TOH1 Output Is at High Level) (2/2) (c) 16-bit timer X1 output control register 0 TX1TOC1 TX1TOC0 TX1TOL1 TX1TOL0 TX1IOC0 0 0 0 0 1 1 0/1 0/1 0: Normal output (low level) 1: Inverted output (high level) Enables timer output Figure 6-40.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (8) PWM output operation (PWM output from TOX00, TOX01, TOX10, and TOX11 when TOH1 output is at high level) A square wave is output from the TOX00, TOX01, TOX10, and TOX11 pins by combining 8-bit timer H1 and 16-bit timers X0 and X1, only when the TOH1 output is at high level. See (1) PWM output operation (single output) through (4) PWM output operation (TMX0 and TMX1 synchronous start mode) for the setting of outputting a square wave.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-41. Example of Register Settings for PWM Output Operation (TMX0 and TMX1 synchronous start/clear mode, PWM Output from TOX00, TOX01, TOX10, and TOX11 When TOH1 Output Is at High Level) (2/2) (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0 TXnTOL1 TXnTOL0 TXnIOC0 0 0 0 0 1 1 0/1 0/1 0: Normal output (low level) 1: Inverted output (high level) Enables timer output Remark n = 0, 1 Figure 6-42.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.6 Interlocking Function with Comparator or INTP0 16-bit timers X0 and X1 can control PWM waveforms by interlocking with the output of comparators 0 to 2 or the INTP0 input signal, without involving the CPU. TMX0 and TMX1, comparators 0 to 2, and INTP0 can be combined as follows.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-44. Block Diagram of 16-Bit Timer X1 Output Configuration Output latch (P33) PM33 Note1 TOTX1C0 Level controller TOTX1C1 TOX10/P33 Output latch (P34) PM34 Note1 TOTX1C2 Level controller TOTX1C3 TOX11/P34 Note2 Mode selector Timer counter clear signal Timer clear controller Comparator 0 output Note2 Mode selector Capture trigger signal Comparator 1 output INTTMX1 Figure 6-45.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-46. Example of Register Settings for Interlocking mode 1 (timer reset mode)  Using CMP2 and INTP0 as triggers TX0CTL3 0 0 0 0 0 1 0 1 Uses CMP2 as trigger Uses INTP0 as trigger Remark When interlocking the timers with either CMP2 or INTP0, set all bits of CMP2 or INTP0, whichever is not used, to 0.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (2) Interlocking mode 2 (timer restart mode) This mode restarts the corresponding timer when the rising edge of the comparators 0 to 2 outputs or the INTP0 input is detected. Figure 6-48.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-49.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) Interlocking mode 3 (timer output reset mode) This mode sets the output of the corresponding timer to the reset state from when the rising edge of the comparators 0 to 2 outputs or the INTP0 input is detected until the next interrupt is generated. Caution Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode. Figure 6-50.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-51.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (4) Priority when multiple interlocking modes occur If multiple interlocking modes have been specified for TMX0 or TMX1, the priority order is as follows: Interlocking mode 1 > Interlocking mode 2 > Interlocking mode 3 (a) Priority of interlocking modes 1 and 2 If interlocking modes 1 and 2 occur at the same time, or if interlocking mode 2 occur while the timer is being reset in interlocking mode 1, interlocking mode 1 has priority and interlocking mode 2 is inva
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (b) Priority of interlocking modes 1 and 3 If interlocking modes 1 and 3 occur at the same time, or if interlocking mode 3 occur while the timer is being reset in interlocking mode 1, interlocking mode 1 has priority and interlocking mode 3 is invalid. Figure 6-53.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7 High-Impedance Output Control Function The high-impedance output control function changes the outputs of 16-bit timers X0 and X1 to a high-impedance state at the generation of an external interrupt input (INTP0) or comparator output (INTCMP0 to INTCMP2) and executes functions such as the PWM output emergency stop function. 6.7.1 Configuration of High-Impedance Output Controller The high-impedance output control circuit includes the following hardware.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7.2 Registers Controlling High-Impedance Output Controller Registers used to control the High-Impedance Output Controller are shown below.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (2) High-impedance output mode select register (HIZTRS) HIZTRS is a register that selects the signal to be used as the high-impedance control trigger and the pin to be set to the high-impedance output state. HIZTRS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears HIZTRS to 00H. Figure 6-57.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) High-impedance output function control register 0 (HZA0CTL0) HZA0CTL0 is a register that controls the high-impedance state of the output buffers. HZA0CTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears HZA0CTL0 to 00H. Figure 6-58.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-58. Format of High-impedance Output Function Control Register 0 (HZA0CTL0) (2/2) HZA0DCT0 High-impedance output trigger bit Notes1 to 4 0 Does not operate. 1 Sets target pin to high-impedance output state and sets (1) HZA0DCF0 bit. HZA0DCC0 High-impedance output control clear bit Notes2 to 6 0 Does not operate. 1 Enables output of target pin and clears (0) HZA0DCF0 bit.
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7.3 High-impedance output control circuit setting procedure (1) Transitioning to the high-impedance output state by detecting the valid edge of the INTP0 input or the output of comparators 0 to 2 <1> Set the HIZTRS1, HSTRS0, and HIZPTS3 to HIZPTS0 bits (select the trigger source and the high-impedance target pin). <2> Set the HZA0DCM0, HZA0DCN0, and HZA0DCP0 bits (select the high-impedance state release condition and valid edge).
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78K0/Ix2 CHAPTER 6 16-BIT TIMERS X0 AND X1 (4) Transitioning to the high-impedance output state by using the HZA0DCT0 bit To set the pin to the high-impedance output state by using the HZA0DCT0 bit, the HZA0DCT0 bit must be set (1) while the trigger signal is in the inactive-level state. When not using the trigger signal (HZA0DCN0 = HZA0DCP0 = 0), however, the high-impedance output state can be entered by setting (1) the HZA0DCT0 bit.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 is mounted onto all 78K0/Ix2 microcontroller products. 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval. (2) Square-wave outputNote 16-bit timer/event counter 00 can output a square wave with any selected frequency.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 7-1.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined. 3.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010) CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by using CRC00. Change the value of CR000 while the timer is stopped (TMC003 and TMC002 = 00). The value of CR010 can be changed during operation if the value has been set in a specific way. For details, refer to 7.5.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H After reset: 0000H R/W FF15H 15 14 13 12 11 FF14H 10 9 8 7 6 5 4 3 2 1 0 CR010 (i) When CR010 is used as a compare register The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM010) is generated if they match.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Timer counter clear TM00 register Compare register set value (0000H) Operation Timer operation enable bit disabled (00) (TMC003, TMC002) Operation enabled (other than 00) Interrupt request signal Interrupt signal is not generated Interrupt signal is generated Remarks 1. N: CR000 register set value, M: CR010 register set value 2. For details of the operation enable bits (bits 3 and 2 (TMC003 and TMC002)), refer to 7.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Table 7-2.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-5.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-6.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) Note TOC00 is an 8-bit register that controls the TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation. However, TOC004 can be rewritten during timer operation as a means to rewrite CR010 (refer to 7.5.1 Rewriting CR010 during TM00 operation).
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software 0  1 One-shot pulse output The value of this bit is always “0” when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PRM00 to 00H. Cautions 1.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-9.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (5) Port alternate switch control register (MUXSEL) This register assigns the pin function. The timer input (TI000) function can be assigned to the P121 or P125 pin of the 78K0/IY2 and the P121 pin of the 78K0/IA2 and 78K0/IB2. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 7-10.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (6) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM0 to FFH.  78K0/IA2, 78K0/IB2 (32 pins) When using the P00/TI000/INTP0// pin for timer input, set PM00 to 1. At this time, the output latch of P00 may be 0 or 1.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4 Operation of 16-Bit Timer/Event Counter 00 7.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock. When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H and a match interrupt signal (INTTM000) is generated.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-15. Example of Software Processing for Interval Timer Function N N N TM00 register 0000H Operable bits (TMC003, TMC002) 00 11 CR000 register N INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, CR000 register, port setting TMC003, TMC002 bits = 11 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.2 Square-wave output operation (78K0/IB2 (30 pins) only) When 16-bit timer/event counter 00 operates as an interval timer (refer to 7.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear & start mode entered upon a match between TM00 and CR000), the counting operation is started in synchronization with the count clock.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-18. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-19.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1). Setting CR000 to 0000H is prohibited.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-22.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-24.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 7-25.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-26.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 7-27.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-28.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-28.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 7-29.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-30.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-30.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 0 OVF00 0/1 0 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 and valid edge of TI000 pin. Clears and starts at valid edge input of TI000 pin.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-31.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-32.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-34.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-36.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 7-37.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-38.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-38.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0 1 0/1 OVF00 0 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 valid edge of TI000 pin.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-39.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-40.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.6 PPG output operation (78K0/IB2 (30 pins) only) A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-42. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-42. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00. The count value of TM00 is cleared.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-43.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.7 One-shot pulse output operation (78K0/IB2 (30 pins) only) A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 0 OVF00 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output. When the value of TM00 matches that of CR000, an interrupt signal (INTTM000) is generated and the TO00 output level is inverted.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-46.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, TOC00 registerNote, CR000, CR010 registers, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits. Starts count operation <2> One-shot trigger input flow TOC00.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 A pulse width can be measured in the following three ways.  Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode)  Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode)  Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Remarks 1. For the setting of the I/O pins, refer to 7.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin. When the valid edge of the TI000 pin is detected, the count value of TM00 is captured to CR010.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-52. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 0 OVF00 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 0 0 0 0 0 1 0/1 1 1: CR000 used as capture register 0: TI010 pin is used as capture trigger of CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-52. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-53.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-53. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.5 Special Use of TM00 7.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the 78K0/Ix2 microcontrollers when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00). However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if CR010 is used for PPG output and the duty factor is changed.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 7-54. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit Setting TOC00.LVS00, LVR00 bits Setting TMC00.TMC003, TMC002 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS00 and LVR00 following steps <1>, <2>, and <3> above.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 7-3 shows the restrictions for each channel. Table 7-3.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000.  Set CR000 to FFFFH.  When TM00 matches CR000 and TM00 is cleared from FFFFH to 0000H Figure 7-58.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
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78K0/Ix2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (12) Reading of 16-bit timer counter 00 (TM00) TM00 can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. Figure 7-59.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.1 Functions of 8-Bit Timer/Event Counter 51 8-bit timer/event counter 51 is mounted onto all 78K0/Ix2 microcontroller products. 8-bit timer/event counter 51 has the following functions.  Interval timer  External event counter 8.2 Configuration of 8-Bit Timer/Event Counter 51 8-bit timer/event counter 51 includes the following hardware. Table 8-1.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus TI51/P30/ TOH1/INTP1 fPRS fPRS/2 fPRS/24 fPRS/26 fPRS/28 8-bit timer H1 output Selector Match INTTM51 Mask circuit 8-bit timer compare register 51 (CR51) 8-bit timer counter 51 (TM51) 3 Clear TCE51 TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) 8-bit timer mode control register 51 (TMC51) Internal bus Remarks 1.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (2) 8-bit timer compare register 51 (CR51) CR51 can be read and written by an 8-bit memory manipulation instruction. The value set in CR51 is constantly compared with the 8-bit timer counter 51 (TM51) count value, and an interrupt request (INTTM51) is generated if they match. The value of CR51 can be set within 00H to FFH. Reset signal generation clears CR51 to 00H. Figure 8-3.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (1) Timer clock selection register 51 (TCL51) This register sets the count clock of 8-bit timer/event counter 51 and the valid edge of the TI51 pin input. TCL51 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TCL51 to 00H. Figure 8-4.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (2) 8-bit timer mode control register 51 (TMC51) TMC51 is a register that controls the 8-bit timer counter 51 (TM51) count operation. TMC51 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-5.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (4) Port mode registers 0 and 3 (PM0, PM3) These registers set ports 0 and 3 input/output in 1-bit units. PM0 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.  78K0/IY2 When using the /P34/TOX11//INTP4 pin for timer input, set PM34 to 1. The output latch of P34 at this time may be 0 or 1.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.4 Operation of 8-Bit Timer/Event Counter 51 8.4.1 Operation as interval timer 8-bit timer/event counter 51 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 51 (CR51). When the count value of 8-bit timer counter 51 (TM51) matches the value set to CR51, counting continues with the TM51 value cleared to 0 and an interrupt request signal (INTTM51) is generated.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 Figure 8-9. Interval Timer Operation Timing (2/2) (b) When CR51 = 00H t Count clock TM51 00H 00H 00H CR51 00H 00H TCE51 INTTM51 Interval time (c) When CR51 = FFH t Count clock TM51 CR51 01H FFH FEH FFH 00H FEH FFH FFH 00H FFH TCE51 INTTM51 Interrupt acknowledged Interrupt acknowledged Interval time R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI51 pin by 8-bit timer counter 51 (TM51). TM51 is incremented each time the valid edge specified by timer clock selection register 51 (TCL51) is input. Either the rising or falling edge can be selected.
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78K0/Ix2 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.5 Cautions for 8-Bit Timer/Event Counter 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 51 (TM51) are started asynchronously to the count clock. Figure 8-11.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 CHAPTER 9 8-BIT TIMER H1 9.1 Functions of 8-Bit Timer H1 8-bit timer H1 is mounted onto all 78K0/Ix2 microcontroller products. 8-bit timer H1 has the following functions.  Interval timer  Square-wave output  PWM output  Carrier generator 9.2 Configuration of 8-Bit Timer H1 8-bit timer H1 includes the following hardware. Table 9-1.
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R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP01 with the count value of the 8-bit timer counter H1 and, when the two values match, generates an interrupt request signal (INTTMH1) and inverts the output level of TOH1.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 9.3 Registers Controlling 8-Bit Timer H1 The following five registers are used to control 8-bit timer H1.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-4.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Cautions 4. With the 78K0/IY2, the actual output of the /P34/TOX11//INTP4 pin is determined by PM34 and P34, in addition to the TOH1 output. 5. With the 78K0/IA2 or 78K0/IB2 (32 pins), the actual output of the /P00/TI000//INTP0 pin or /P34/TOX11//INTP4 pin is determined by PM00 and P00 or PM34 and P34, in addition to the TOH1 output. 6.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 (3) Port alternate switch control register (MUXSEL) This register assigns the pin function. The timer output (TOH1) can be assigned to P34 of the 78K0/IY2 and P00 or P34 of 78K0/IA2 and 78K0/IB2 (32 pins). This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 9-6.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 (4) Port mode registers 0 and 3 (PM0, PM3) These registers set ports 0 and 3 input/output in 1-bit units. PM0 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.  78K0/IY2 When using the /P34/TOX11//INTP4 pin for timer output, clear PM34 and the output latch of P34 to 0.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 9.4 Operation of 8-Bit Timer H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and the 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode. Since a match of the 8-bit timer counter H1 and the CMP11 register is not detected even if the CMP11 register is set, timer output is not affected.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-10.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1 00H CMP01 00H TMHE1 INTTMH1 TOH1 Interval time R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited. The 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register during timer operation is possible. The operation in PWM output mode is as follows.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows.  PWM pulse output cycle = (N + 1)/fCNT  Duty = (M + 1)/(N + 1) Cautions 1.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H CMP01 A5H CMP11 01H A5H 00H 01H 02H A5H 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <2> <3> <4> TOH1 (TOLEV1 = 1) <1> The count operation is enabled by setting the TMHE1 bit to 1. Start the 8-bit timer counter H1 by masking one count clock to count up. At this time, PWM output outputs an inactive level.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP01 FFH CMP11 00H FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, CMP11 = FEH Count clock 8-bit timer counter H1 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP01 FFH CMP11 FEH FEH FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP01 01H CMP11 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H  03H, CMP01 = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H (03H) 02H CMP11 <2> 03H <2>’ TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHE1 = 1. Start the 8-bit timer counter H1 by masking one count clock to count up.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 9.4.3 Carrier generator operation In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Setting <1> Set each register. Figure 9-14.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows.  Carrier clock output cycle = (N + M + 2)/fCNT  Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-15.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-15.
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78K0/Ix2 CHAPTER 9 8-BIT TIMER H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>’ M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer is mounted onto all 78K0/Ix2 microcontroller products. The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 10-2.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 10-2.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H).  Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, refer to CHAPTER 24).
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) Watchdog timer operation stops. In HALT mode Watchdog timer operation continues.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows.  If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again.  Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated.
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78K0/Ix2 CHAPTER 10 WATCHDOG TIMER 17 Remark If the overflow time is set to 2 /fIL, the window close time and open time are as follows. Setting of Window Open Period 25% 50% 75% 100% Window close time 0 to 3.64 s 0 to 2.43 s 0 to 1.21 s None Window open time 3.64 to 3.97 s 2.43 to 3.97 s 1.21 to 3.97 s 0 to 3.97 s  Overflow time: 217/fIL (MAX.) = 217/33 kHz (MAX.) = 3.97 s  Window close time: 0 to 217/fIL (MIN.)  (1  0.25) = 0 to 217/27 kHz (MIN.)  0.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER Item 10-bit A/D converter 78K0/IY2 78K0/IA2 16 pins 20 pins 5 ch 6 ch 78K0/IB2 30 pins 32 pins 9 ch 11.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to 9 channels (ANI0 to ANI8) with a resolution of 10 bits. In products with operational amplifier, ANI1 functions alternately as operational amplifier output (AMPOUT)/PGA input (PGAIN).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 Comparison voltage generator Sample & hold circuit ANI1/P21/AMPOUT Note1 A/D voltage comparator ANI2/P22 ANI3/P23 ADCE bit Selector ANI4/P24 ANI5/P25 ANI6/P26 AVSS Successive approximation register (SAR) ANI7/P27 AVSS ANI8/P70 Selector PGA output Note2 Internal voltage 1.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI8 pins These are the analog input pins of the 9-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. Remark A/D converter analog input pins differ depending on products.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (8) 8-bit A/D conversion result register L (ADCRL) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the lower 8 bits of the A/D conversion result.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following six registers.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (only A/D voltage comparator consumes power) 1 0 Setting prohibited 1 1 Conversion mode (A/D voltage comparator operation) Figure 11-3.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection (1/2) (1) 4.0 V  AVREF  5.5 V A/D Converter Mode Register 0 Conversion Time Selection Mode Conversion (ADM0) FR2 FR1 FR0 Clock (fAD) LV1 LV0 fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz fPRS = 20 MHz (when using PLL) 264/fPRS 66.0 s 33.0 s 26.4 s 13.2 s fPRS/12 1 176/fPRS 44.0 s 22.0 s 17.6 s 8.8 s fPRS/8 1 0 132/fPRS 33.0 s 16.5 s 13.2 s 6.6 s fPRS/6 1 1 88/fPRS 22.0 s 11.0 s 8.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection (2/2) (2) 2.7 V  AVREF < 4.0 V A/D Converter Mode Register 0 Conversion Time Selection Mode Conversion (ADM0) FR2 FR1 FR0 Clock (fAD) LV1 LV0 fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz fPRS = 20 MHz (when using PLL) 0 0 0 0 0 1 0 0 Normal 264/fPRS 66.0 s 33.0 s 26.4 s 13.2 s fPRS/12 176/fPRS 44.0 s 22.0 s 17.6 s Setting fPRS/8 13.2 s prohibited fPRS/6 0 1 0 132/fPRS 33.0 s 16.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-4. A/D Converter Sampling and A/D Conversion Timing ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD SAR clear Wait periodNote Sampling Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, refer to CHAPTER 31 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) ADCR is a 16-bit register that stores the A/D conversion result.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (3) 8-bit A/D conversion result register L (ADCRL) ADCRL is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are stored. ADCRL can be read by an 8-bit memory manipulation instruction. Reset signal generation clears ADCRL to 00H. Figure 11-6. Format of 8-Bit A/D Conversion Result Register L (ADCRL) Address: FF08H Symbol 7 After reset: 00H 6 R 5 4 3 2 1 0 ADCRL Cautions 1.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (5) 10-bit A/D conversion result register for TMXn synchronization (ADCRXn) ADCRXn is a 16-bit register that holds the A/D conversion result when A/D conversion is started with the output of 16bit timer Xn as the trigger. The higher 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-9. Format of 8-bit A/D conversion result register L for TMXn synchronization (ADCRXnL) Address: FF16H (ADCRX0L), FF18H (ADCRX1L) Symbol ADCRXnL (n = 0, 1) 7 6 5 4 After reset: 00H 3 R 2 1 0 Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCRXnL may become undefined.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-10.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (8) A/D port configuration registers 0, 1 (ADPC0, ADPC1) ADPC0 switches the P20/AMP-/ANI0 to P27/ANI7 pins to digital I/O or analog input of port. Each bit of ADPC0 corresponds to a pin of port 2 and can be specified in 1-bit units. ADPC1 switches the ANI8/P70 pin to digital I/O or analog input of port. Each bit of ADPC1 corresponds to a pin of P70 in port 1 and can be specified in 1-bit units.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-12. Format of A/D Port Configuration Register 1 (ADPC1) (78K0/IB2 Only) Address: FF2FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC1 0 0 0 0 0 0 0 ADPC8 ADPCS8 Digital I/O or analog input selection 0 Analog input 1 Digital I/O Cautions 1. Set the pin set to analog input to the input mode by using port mode register 7 (PM7). 2. If data is written to ADPC1, a wait cycle is generated.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-13. Format of Port Mode Register 2 (PM2) (1) 78K0/IY2 Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 PM25 PM24 PM23 PM22 0 PM20 Caution Be sure to set bits 1, 6 and 7 of PM2 to 1. (2) 78K0/IA2 Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 Caution Be sure to set bits 6 and 7 of PM2 to 1.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER When using P20/AMP-/ANI0 to P27/ANI7, and P70/ANI8, set the registers according to the pin function to be used (refer to Tables 11-3 to 11-8). Table 11-3. Setting Functions of P20/ANI0/AMP-, P22/ANI2/AMP+ Pins ADPC0 OPAMP0E Note bit PM2 Register Register Digital I/O  Input mode selection  Output mode Analog input Input mode 0 selection 1 ADS Register P20/ANI0/AMP-, (n = 0, 2) P22/ANI2/AMP+ Pins Selects ANIn. Setting prohibited Does not select ANIn.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-4. Setting Functions of P21/ANI1/AMPOUT/PGAIN Pin ADPC0 PM2 Register Register Digital OPAMP0E Note bit Input mode PGAEN  0 I/O selection 1  Output mode 0  Input mode 0 0 selection 0 P21/ANI1/AMPOUT/PGAIN Pin Selects ANI1. Setting prohibited Does not select ANI1. Digital input  Setting prohibited Selects ANI1. Setting prohibited Does not select ANI1.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-5. Setting Functions of P23/ANI3/CMP2+, P24/ANI4/CMP0+, P25/ANI5/CMP1+ Pins ADPC0 PM2 Register CMPmEN bit ADS Register P23/ANI3/CMP2+, P24/ANI4/CMP0+, (m = 0 to 2) (n = 3 to 5) P25/ANI5/CMP1+ Pins Register Digital I/O  Input mode Selects ANIn. Setting prohibited Does not select ANIn. Digital input Selects ANIn. Setting prohibited Does not select ANIn. Digital output 0 Selects ANIn.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Table 11-7. Setting Functions of P27/ANI7 Pin ADPC0 Register Digital I/O selection PM2 Register Input mode Output mode Analog input Input mode selection ADS Register Selects ANI7. Setting prohibited Does not select ANI7. Digital input Selects ANI7. Setting prohibited Does not select ANI7. Digital output Selects ANI7. Analog input (to be converted into digital signal) Does not select ANI7.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.4 Operation of A/D Converter 11.4.1 Basic operation of A/D converter (software trigger mode) <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1 to start the operation of the A/D voltage comparator.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Cautions 1. Make sure the period of <2> to <6> is 1 s or more. 2. If the timing of <2> is earlier than that of <5>, <2> may be performed any time. 3. When switching from software trigger mode to timer trigger mode, switch the operation mode 4. To select the internal voltage (1.2 V) as an analog input, set the ADCS bit to 1 when at least 10 s and input channel after stopping the A/D conversion operation (clearing (0) ADCS).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.4.2 Basic operation of A/D converter (timer trigger mode) <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1 to start the operation of the A/D voltage comparator.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Cautions 1. Make sure the period of <2> to <7> is 1 s or more. 2. If the timing of <2> is earlier than that of <6>, <2> may be performed any time. 3. When switching from timer trigger mode to software trigger mode, switch the operation mode 4. To select the internal voltage (1.2 V) as an analog input, set the ADCS bit to 1 when at least 10 s and input channel after stopping the A/D conversion operation (clearing (0) ADCS).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.4.3 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI8) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN AVREF  1024 + 0.5) or (ADCR  0.5)  where, INT( ): AVREF 1024  VAIN < (ADCR + 0.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-17 shows the relationship between the analog input voltage and the A/D conversion result. Figure 11-17. Relationship between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 03FFH 1022 03FEH 1021 03FDH 3 0003H 2 0002H 1 0001H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.4.4 A/D converter trigger mode selection Two trigger modes for setting the A/D conversion start timing are available. These trigger modes are set by using the analog input channel specification register (ADS).  Software trigger mode  Timer trigger mode (1) Software trigger mode If a normal start is set by setting the ADTRG0 and ADTRG1 bits, A/D conversion of the analog input channel selected by ADS will be started by setting ADCS = 1.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-18. A/D Conversion Operation A/D conversion is startedNote 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result immediately before is retained A/D conversion result registerNote 2 ANIn ANIn Stopped Conversion result immediately before is retained ANIm INTAD Notes 1. Software trigger mode: Timer trigger mode: A/D conversion is started by setting (1) ADCS.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER The setting methods are described below.  Software trigger mode <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1. <3> Set the channel to be used to analog input by using the A/D port configuration registers 0 and 1 (ADPC0, ADPC1) and port mode registers 2 and 7 (PM2, PM7).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER  Timer trigger mode <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1. <3> Set the channel to be used to analog input by using the A/D port configuration registers 0 and 1 (ADPC0, ADPC1) and port mode registers 2 and 7 (PM2, PM7).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale  3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER 11.6 Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the power supply current in STOP mode, clear bits 7 (ADCS) and 0 (ADCE) of A/D converter mode register 0 (ADM0) to 0 before executing a STOP instruction. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. (2) Input range of ANI0 to ANI8 Observe the rated range of the ANI0 to ANI8 input voltage.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER Figure 11-25. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI8 C = 100 to 1,000 pF AVSS VSS (5) ANI0/P20 to ANI7/P27 and ANI8/P70 <1> The analog input pins (ANI0 to ANI7 and ANI8) are also used as digital I/O port pins (P20 to P27 and P70).
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
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78K0/Ix2 CHAPTER 11 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-27. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 11-9. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF Mode R1 C1 C2 4.0 V  AVREF  5.5 V Normal 5.2 k 8 pF 6.3 pF High-speed 1 5.2 k High-speed 2 7.8 k Normal 18.6 k High-speed 2 7.8 k 2.7 V  AVREF < 4.0 V Remarks 1.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER CHAPTER 12 OPERATIONAL AMPLIFIER Item 78K0/IY2 78K0/IA2 16 Pins 20 Pins Operational amplifier (products with 1 ch (PGA mode operational amplifier only) only) 78K0/IB2 30 Pins 32 Pins 1 ch (Single AMP mode and PGA mode) 12.1 Function of Operational Amplifier Operational amplifier is mounted onto products with operational amplifier of the 78K0/Ix2 microcontrollers. The operational amplifier has the following modes.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER 12.2 Configuration of Operational Amplifier The operational amplifier 0 consists of the following hardware. Table 12-1.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER 12.3 Registers Used in Operational Amplifier The operational amplifier uses the following four registers.  Operational amplifier 0 control register (AMP0M)  A/D port configuration registers 0 (ADPC0)  Analog input channel specification register (ADS)  Port mode register 2 (PM2) (1) Operational amplifier 0 control register (AMP0M) AMP0M controls the operations of operational amplifier. AMP0M can be set by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER Cautions 2. When using the single AMP mode, use the ADPC0 register to select the AMPOUT/PGAIN/ANI1/P21, AMP-/ANI0/P20, and AMP+/ANI2/P22 pins as analog inputs. 3. When using as digital inputs the pins of port 2, which are not used with the operational amplifier, when the operational amplifier is used, make sure that the input levels of digital input ports are fixed to prevent degradation of the A/D conversion resolution.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER (3) Analog input channel specification register (ADS) ADS specifies the input channel of the analog voltage to be A/D converted and sets the A/D conversion start method. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ADS to 00H. Figure 12-4.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2 and 7 (PM2, PM7). 2. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set ADS after single AMP operation setting when selecting the operational amplifier output signal as analog input. 3. To select the internal voltage (1.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER When using P20/ANI0/AMP-, P21/ANI1/AMPOUT/PGAIN, and P22/ANI2/AMP+, set the registers according to the pin function to be used (refer to Tables 12-2 and 12-3). Table 12-2. Setting Functions of P20/ANI0/AMP-, P22/ANI2/AMP+ Pins ADPC0 PM2 Register Register Digital I/O OPAMP0E Note bit  Input mode selection  Output mode Analog input Input mode 0 selection 1 ADS Register P20/ANI0/AMP-, (n = 0, 2) P22/ANI2/AMP+ Pins Selects ANIn.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER Table 12-3. Setting Functions of P21/ANI1/AMPOUT/PGAIN Pin ADPC0 PM2 Register Register Digital Input mode OPAMP0E Note bit PGAEN  0 I/O selection 1  Output mode 0  Input mode 0 0 selection 0 P21/ANI1/AMPOUT/PGAIN Pin Selects ANI1. Setting prohibited Does not select ANI1. Digital input  Setting prohibited Selects ANI1. Setting prohibited Does not select ANI1.
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78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER 12.4 Operation of Operational Amplifier The operational amplifier has the following mode.  Single AMP mode  PGA (Programmable gain amplifier) mode 12.4.1 Single AMP mode Operational amplifier has two input pins (the AMP- pin and the AMP+ pin) and one output pin (the AMPOUT pin), and can be used as single-power supply amplifier that can be externally connected.
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78K0/Ix2 CHAPTER 13 COMPARATORS CHAPTER 13 COMPARATORS 13.1 Features of Comparators Comparators are mounted onto all 78K0/Ix2 microcontroller products. Comparators have the following functions. • Comparators are equipped with three channels (comparators 0 to 2). • The following reference voltages can be selected. <1> Internal reference voltage: 3 (reference voltage level: 1.58 V (TYP.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-1.
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78K0/Ix2 CHAPTER 13 COMPARATORS 13.2 Configuration of Comparators The comparators consist of the following hardware. Table 13-1. Configuration of Comparators Item Control registers Configuration Comparator n control register (CnCTL) DAn internal reference voltage selection register (CnRVM) Comparator output flag register (CMPFLG) A/D configuration register 0 (ADPC0) Port mode register 2 (PM2) Port register 2 (P2) 13.3 Registers Controlling Comparators The comparators use the following five registers.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-2.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-3.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-4.
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78K0/Ix2 CHAPTER 13 COMPARATORS (2) DAn internal reference voltage selection register (CnRVM) CnRVM is used to set the internal reference voltage level of comparator. CnRVM also controls the internal reference voltage generation operation by using bit 7 (CVRE) of C0RVM. CnRVM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CnRVM to 00H. R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-5. Format of DA0 Internal Reference Voltage Selection Register (C0RVM) Address: FF63H After reset: 00H R/W Symbol <7> 6 5 <4> <3> <2> <1> <0> C0RVM CVRE 0 0 C0VRS4 C0VRS3 C0VRS2 C0VRS1 C0VRS0 CVRE Internal reference voltage generation operation control 0 Stops operation 1 Enables operation C0VRS4 C0VRS3 C0VRS2 C0VRS1 C0VRS0 0 0 0 0 0 0.05 V (TYP.) 0 0 0 0 1 0.1 V (TYP.) 0 0 0 1 0 0.15 V (TYP.) 0 0 0 1 1 0.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-6. Format of DA1 Internal Reference Voltage Selection Register (C1RVM) Address: FF65H After reset: 00H R/W Symbol 7 6 5 <4> <3> <2> <1> <0> C1RVM 0 0 0 C1VRS4 C1VRS3 C1VRS2 C1VRS1 C1VRS0 C1VRS4 C1VRS3 C1VRS2 C1VRS1 C1VRS0 0 0 0 0 0 0.05 V (TYP.) 0 0 0 0 1 0.1 V (TYP.) 0 0 0 1 0 0.15 V (TYP.) 0 0 0 1 1 0.2 V (TYP.) 0 0 1 0 0 0.25 V (TYP.) 0 0 1 0 1 0.3 V (TYP.) 0 0 1 1 0 0.35 V (TYP.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-7. Format of DA2 Internal Reference Voltage Selection Register (C2RVM) Address: FF67H After reset: 00H R/W Symbol 7 6 5 <4> <3> <2> <1> <0> C2RVM 0 0 0 C2VRS4 C2VRS3 C2VRS2 C2VRS1 C2VRS0 C2VRS4 C2VRS3 C2VRS2 C2VRS1 C2VRS0 0 0 0 0 0 0.05 V (TYP.) 0 0 0 0 1 0.1 V (TYP.) 0 0 0 1 0 0.15 V (TYP.) 0 0 0 1 1 0.2 V (TYP.) 0 0 1 0 0 0.25 V (TYP.) 0 0 1 0 1 0.3 V (TYP.) 0 0 1 1 0 0.35 V (TYP.
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78K0/Ix2 CHAPTER 13 COMPARATORS (3) Comparator output flag register (CMPFLG) CMPFLG indicates the comparator output level. CMPFLG is read-only by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CMPFLG to 00H. Figure 13-8.
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78K0/Ix2 CHAPTER 13 COMPARATORS (4) A/D port configuration register 0 (ADPC0) ADPC0 switches the P20/AMP-/ANI0 to P27/ANI7 pins to digital I/O or analog input of port. Each bit of ADPC0 corresponds to a pin of port 2 and can be specified in 1-bit units. When CMP0+/P24/ANI4, CMP1+/P25/ANI5, and CMP2+/P23/ANI3 pins, and CMPCOM/P26/ANI6 pin Note are used for the comparator input and comparator common input respectively, set these pins to analog input by ADPC0.
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78K0/Ix2 CHAPTER 13 COMPARATORS (5) Port mode register 2 (PM2) PM2 is used to set port 2 input or output in 1-bit units. When CMP0+/P24/ANI4, CMP1+/P25/ANI5, and CMP2+/P23/ANI3 pins, and CMPCOM/P26/ANI6 pin Note are used for the comparator input and comparator common input respectively, set PM23 to PM25, PM26 bits to 1. The output latches of P23 to P25, P26 at this time may be 0 or 1. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 to FFH.
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78K0/Ix2 CHAPTER 13 COMPARATORS When using P23/ANI3/CMP2+, P24/ANI4/CMP0+, P25/ANI5/CMP1+, P26/ANI6/CMPCOM, set the registers according to the pin function to be used (refer to Tables 13-2 and 13-3). Table 13-2.
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78K0/Ix2 CHAPTER 13 COMPARATORS 13.4 Operation of Comparators 13.4.1 Starting comparator operation (using internal reference voltage for comparator reference voltage) Figure 13-11. Example of Setting Procedure when Starting Comparator Operation (Using Internal Reference Voltage for Comparator Reference Voltage) Start ADPC0 register setting Setting the pin to be used as a comparator input to analog input. PM2 register setting Setting the pin to be used as a comparator input to input mode.
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78K0/Ix2 CHAPTER 13 COMPARATORS Figure 13-12. Example of Setting Procedure when Changing Internal Reference Voltage Start CnOE bit setting CnRVM register setting CnOE bit settingNote Clearing (0) the CnOE bit of CnCTL and disabling the comparator output. Changing the internal reference voltage level by using the CnVRS0 to CnVRS4 bits of CnRVM. Setting (1) the CnOE bit of CnCTL and enabling the comparator output.
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78K0/Ix2 CHAPTER 13 COMPARATORS 13.4.3 Stopping comparator operation Figure 13-14. Example of Setting Procedure when Stopping Comparator Operation Operation in progress CnOE bit setting Clear (0) the CnOE bit of CnCTL. CMPnEN bit setting Clear (0) the CMPnEN bit of CnCTL. CVRE bit settingNote Clear (0) the CVRE bit of C0RVM.Note Operation stop Note Only when using the internal reference voltage. R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI CHAPTER 14 SERIAL INTERFACE UART6/DALI Item 78K0/IY2 78K0/IA2 16 pins 20 pins 78K0/IB2 30 pins  Serial interface UART6/DALI 32 pins  Remark : Mounted, : Not mounted 14.1 Functions of Serial Interface UART6/DALI Serial interface UART6/DALI has the following three modes.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Cautions 3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-2. LIN Reception Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field 13-bit SBF reception SF reception ID reception Data reception Data reception LIN Bus <5> <2> RXD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Selector Figure 14-3. Port Configuration for LIN Reception Operation P61/SDAA0/RxD6 RXD6 input Port mode (PM61) P00/INTP0/TI000 Port mode (PM00) INTP0 input Port input switch control (ISC0) 0: Select INTP0 (P00) 1: Select RxD6 (P61) Selector Output latch (P00) Selector Selector Output latch (P61) TI000 input Port input switch control (ISC1) 0: Select TI000 (P00) 1: Select RxD6 (P61) Remarks 1.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI The peripheral functions used in the LIN communication operation are shown below.  External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.2 Configuration of Serial Interface UART6/DALI Serial interface UART6/DALI includes the following hardware. Table 14-1.
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R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (1) UART receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by UART/DALI receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.  In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.3 Registers Controlling Serial Interface UART6/DALI Serial interface UART6/DALI is controlled by the following nine registers.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (2) UART/DALI operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6/DALI. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-6. Format of UART/DALI Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (3) UART/DALI reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6/DALI. This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (4) UART transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-9. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz (when using PLL) 0 0 0 0 fPRS 0 0 0 1 fPRS/2 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 2 MHz 5 MHz 10 MHz 20 MHz 1 MHz 2.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (6) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6/DALI. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (7) LIN operation control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Cautions1. 2. ASICL6 is not used in DALI mode (UADLSEL = 1). In DALI mode, even if the SBRT6, SBTT6, SBL62 to SBL60, DIR6, and TXDLV6 bits are set, the set contents are invalid.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-11. Format of LIN Operation Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (8) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1 (refer to Figure 14-3 Port Configuration for LIN Reception Operation). This register can be set by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (10) Port output mode register 6 (POM6) This register sets the output mode of P60 and P61 in 1-bit units. When using the P60/TxD6/SCLA0 pin as the data output of serial interface UART6/DALI, clear POM60 to 0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-14.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.4 Operation of Serial Interface UART6/DALI Serial interface UART6/DALI has the following three modes.  Operation stop mode  Asynchronous serial interface (UART) mode  DALI mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI The relationship between the register settings and pins is shown below. Table 14-2.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-15 and 14-16 show the format and waveform example of the normal transmit/receive data. Figure 14-15. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-16. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (c) Normal transmission When bit 7 (POWER6) of UART/DALI operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to UART/DALI transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to UART/DALI transmit shift register 6 (TXS6).
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (d) Continuous transmission The next transmit data can be written to UART/DALI transmit buffer register 6 (TXB6) as soon as UART/DALI transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-18 shows an example of the continuous transmission processing flow. Figure 14-18. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-19 shows the timing of starting continuous transmission, and Figure 14-20 shows the timing of ending continuous transmission. Figure 14-19. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-20.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of UART/DALI operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 14-21).
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of UART/DALI reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-23, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-23.
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78K0/Ix2 (i) CHAPTER 14 SERIAL INTERFACE UART6/DALI SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of UART/DALI operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.4.3 DALI mode This mode is used to perform slave transmission/reception of DALI (Digital Addressable Lighting Interface). DALI performs communication using the following protocol. (1) Data structure <1> Bit definition A falling edge is bit-defined as “0” and a rising edge as “1”, because DALI communication uses Manchester code. If no communication is performed, DALI communication is fixed to the high level. Figure 14-26.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI  Backward frame This is a frame used when transmitting from the slave to a master. A frame consists of 11 bits. Figure 14-28. Backward-Frame Structure a: Start bit b: Data byte c: Stop bit 1-bit 8-bit 2-bit a b c This indicates the start of the frame. It is always the same waveform as “1”. This replies to the master. This indicates the end of the frame. It is fixed to the high level.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (3) Registers used  UART/DALI mode control register (UADLCTL)  UART/DALI operation mode register 6 (ASIM6)  UART/DALI reception error status register 6 (ASIS6)  Clock selection register 6 (CKSR6)  Baud rate generator control register 6 (BRGC6)  Port mode register 6 (PM6)  Port register 6 (P6)  Port output mode register 6 (POM6) The basic procedure of setting an operation in the DALI mode is as follows.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (4 ) DALI communication (slave transmission/reception) operation procedure An example of DALI slave processing is shown below. <1> Perform initial settings such as of the port I/Os and baud rate (1,200 bps). <2> Wait for a command to be transmitted from the master. <3> After receiving the command from the master, acquire and analyze the command data stored in the DALI receive buffer register (RXBDL).
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-31.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-32. Example of DALI Communication (Slave Transmission) Flow Chart POWER6 bit TXE6 bit Writing data TXB6 register "01100101B" (8-bit data) Baud rate clock Start bit 0 1 1 0 0 1 0 1 Stop bit TXD6 pin INTST6 R01UH0010EJ0500 Rev.5.
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R01UH0010EJ0500 Rev.5.00 Feb 28, 2012 . INTSR6/INTSRE6 RXBDL register Baud rate clock RXD6 pin RXE6 bit POWER6 bit 8-bit 8-bit Start Adress 0 Adress 1 Adress 2 Adress 3 Adress 4 Adress 5 Adress 6 Adress 7 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 (1) (0) (1) (1) (1) (0) (0) (0) bit (1) (0) (1) (1) (1) (0) (0) (0) Stop bit Figure 14-33. Example of DALI Communication (Slave Reception) Flow Chart Receive data(higher 8 bits: adress, lower 8 bits: data) . Adress: 01100101B .
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.4.4 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6/DALI. Separate 8-bit counters are provided for transmission and reception.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Figure 14-34.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI 14.4.5 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression.  UART mode: Baud rate =  DALI mode: Baud rate = fXCLK6 2k fXCLK6 4k [bps] [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (UART mode: k = 4, 5, 6, ..., 255, DALI mode: k = 8, 9, 10, ..., 255) Table 14-5.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate (UART) = 10 M / (2  33) = 10000000 / (2  33) = 151,515 [bps] Error = (151515/153600  1)  100 = 1.357 [%] (3) Example of setting baud rate Table 14-6. Set Data of Baud Rate Generator Baud fPRS = 2.0 MHz fPRS = 5.0 MHz fPRS = 20.0 MHz fPRS = 10.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (4) Permissible baud rate range during reception (UART mode) The permissible error from the baud rate at the transmission destination during reception in UART mode is shown below. Cautions 1. Make sure that the baud rate error during reception in UART mode is within the permissible error range, by using the calculation expression shown below. 2. The allowable error ranges are “baud rate error  25%” and “duty error  12.5%” during reception in DALI mode.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI Minimum permissible data frame length: FLmin = 11  FL  k2 2k  FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
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78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 14-36.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA CHAPTER 15 SERIAL INTERFACE IICA Item Serial interface IICA 78K0/IY2 78K0/IA2 16 pins 20 pins  78K0/IB2 30 pins 32 pins  Remark : Mounted, : Not mounted 15.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-1.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-2 shows a serial bus configuration example. 2 Figure 15-2. Serial Bus Configuration Example Using I C Bus + VDD + VDD Master CPU1 SDAA0 Slave CPU1 Address 0 SCLA0 Serial data bus Serial clock SDAA0 Slave CPU2 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 15-1.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-4. Format of Slave Address Register 0 (SVA0) Address: FFA6H Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 SVA0 0 0Note Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAA0 pin’s output level. (4) Wakeup controller This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the address value set to the slave address register 0 (SVA0) or when an extension code is received.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (1/4) Address: FFA7H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICACTL0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable Note 1 0 Stop operation. Reset the IICA status register 0 (IICAS0) 1 Enable operation. . Stop internal operation. Be sure to set this bit (1) while the SCLA0 and SDLA0 lines are at high level.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUP bit of the IICA control register 1 (IICACTL1) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (3/4) STT0 Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating:  When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (4/4) SPT0 Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing  For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (2) IICA status register 0 (IICAS0) 2 This register indicates the status of I C. This register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICAS0 register while the address match wakeup function is enabled (WUP = 1) in STOP mode is prohibited.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-6. Format of IICA Status Register 0 (IICAS0) (2/3) EXC0 Detection of extension code reception 0 Extension code was not received. 1 Extension code was received.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-6. Format of IICA Status Register 0 (IICAS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-7.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (4) IICA control register 1 (IICACTL1) 2 This register is used to set the operation mode of I C and detect the statuses of the SCLA0 and SDAA0 pins. This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. 2 Set the IICACTL1 register, except the WUP bit, while operation of I C is disabled (bit 7 (IICE0) of IICA control register 0 (IICACTL0) is 0).
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) 0 The SCLA0 pin was detected at low level. 1 The SCLA0 pin was detected at high level.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (5) IICA low-level width setting register (IICWL) This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA being in master mode. This register can be set by an 8-bit memory manipulation instruction. 2 Set this register while operation of I C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0). Reset signal generation sets this register to FFH. Figure 15-9.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (8) Port output mode register 6 (POM6) 2 This register sets the output mode of P60 and P61 in 1-bit units. During I C communication, set POM60 and POM61 to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 15-12.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.4 I2C Bus Mode Functions 15.4.1 Pin configuration The serial clock pin (SCLA0) and serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAA0 .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.4.2 Setting transfer clock by using IICWL and IICWH registers (1) Setting transfer clock on master side fPRS Transfer clock = IICWL + IICWH + fPRS (tR + tF) At this time, the optimal setting values of the IICWL and IICWH registers are as follows. (The fractional parts of all setting values are rounded up.)  When the fast mode 0.52 IICWL = Transfer clock  fPRS 0.48 IICWH = ( Transfer clock  tR  tF)  fPRS  When the normal mode 0.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. Figure 15-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C bus’s serial data bus. 2 Figure 15-15.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 15-20.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 15-21.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-21.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.7 Canceling wait 2 The I C usually cancels a wait state by the following processing.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 0 (IICACTL0) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 15-2. Table 15-2.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (5) Stop condition detection INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1). 15.5.9 Address match detection method 2 In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Table 15-4.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.13 Wakeup function 2 The I C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-24. Flow When Setting WUP = 0 upon Address Match (Including Extension Code Reception) STOP mode state Note No INTIICA0 = 1? Yes WUP = 0 Wait Waits for 5 clocks. Reading IICAS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. Note Perform the processing after “INTIICA0 = 1?” also when an INTIICA0 vector interrupt occurs.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-25. When Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP = 1 Wait Waits for 3 clocks. STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0. Note Yes INTIICA0 = 1? No Interrupt servicing WUP = 0 Wait Waits for 5 clocks. Reading IICAS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-26 shows the communication reservation timing. Figure 15-26.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-28. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note 2 MSTS0 = 0? Yes Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 1) When bit 1 (STT0) of the IICA control register 0 (IICACTL0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.15 Cautions (1) When STCEN (bit 1 of IICA flag register 0 (IICAF0)) = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (the IICBSY flag (bit 6 of the IICAF0 register) = 1) is recognized regardless of the actual bus status.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the 78K0/Kx2-L microcontrollers as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 15-29. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)). Initial setting Setting port IICWL, IICWH ← XXH Sets a transfer clock. SVA0 ← XXH Sets a local address.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 15-30. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)). Setting port IICWL, IICWH ← XXH Selects a transfer clock. SVA0 ← XXH Sets a local address. IICAF0 ← 0XH Setting STCEN and IICRSV Sets a start condition.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-30. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Secure wait timeNote by software. Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIICA0 interrupt occurs? No Waits for bus release (communication being reserved).
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-30. Master Operation in Multi-Master System (3/3) C Writing IICA INTIICA0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IICA INTIICA0 interrupt occurs? INTIICA0 interrupt occurs? No Waits for data transmission.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 2 15.5.17 Timing of I C interrupt request (INTIICA0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the IICAS0 register when the INTIICA0 signal is generated are shown below. Remark ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B 3: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 4: IICAS0 = 1000××00B (Sets SPT0 to 1)Note 5: IICAS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 1 3: IICAS0 = 1000××00B (Clears WTIM0 to 0Note 2, sets STT0 to 1) 4: IICAS0 = 1000×110B 5: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 3 6: IICAS0 = 1000××00B (Sets SPT0 to 1) 7: IICAS0 = 00000
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICAS0 = 1010×110B 2: IICAS0 = 1010×000B 3: IICAS0 = 1010×000B (Sets WTIM0 to 1)Note 4: IICAS0 = 1010××00B (Sets SPT0 to 1) 5: IICAS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0001×000B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICAS0 = 0001×110B 2: IICA
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0001×110B 4: IICAS0 = 0001×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0010×010B 4: IICAS0 = 0010×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match a
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 00000110B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not exte
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code.
PAGE 543
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B 3: IICAS0 = 0001×110B 4: IICAS0 = 0001×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 t
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B 3: IICAS0 = 0010×010B 4: IICAS0 = 0010×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICAS0 = 00100010B 2: IICAS0 = 00100000B 3: IICAS0 = 00000110B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not extens
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICAS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICAS0 = 0101×110B 2: IICAS0 = 0001×100B 3: IICAS0 = 0001××00B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICAS0 = 0110×010B 2: IICAS0 = 0010×000B 3: IICAS0 = 0
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICAS0 = 0110×010B 2: IICAS0 = 0010×110B 3: IICAS0 = 0010×100B 4: IICAS0 = 0010××00B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt reque
PAGE 549
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICAS0 = 0110×010B Sets LREL0 = 1 by software 2: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICAS0 = 10001110B 2: IICAS0 = 0100000
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICAS0 = 10001110B 2: IICAS0 = 01000100B 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICAS0 = 1000×110B 2: IICAS0 = 01000110B 3: I
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICAS0 = 1000×110B 2: IICAS0 = 01100010B Sets LREL0 = 1 by software 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICAS0 = 10000110B 2: IICAS0 = 01000001B Remark : Always generated :
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000×100B (Clears WTIM0 to 0) 4: IICAS0 = 01000000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT0
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000××00B (Sets STT0 to 1) 4: IICAS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000×100B (Clears WTIM0 to 0) 4: IICAS0 = 01000100B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 SPT0 =
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA 15.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICAS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 CHAPTER 16 SERIAL INTERFACE CSI11 Item 78K0/IY2 78K0/IA2 16 pins 20 pins 78K0/IB2 30 pins  Serial interface CSI11 32 pins  Remark : Mounted, : Not mounted 16.1 Functions of Serial Interface CSI11 Serial interface CSI11 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, refer to 16.4.1 Operation stop mode.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-1.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (2) Serial I/O shift register 11 (SIO11) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO11 if bit 6 (TRMD11) of serial operation mode register 11 (CSIM11) is 0. During reception, the data is read from the serial input pin (SI11) to SIO11. Reset signal generation clears this register to 00H.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-2. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 0 Disables operation 1 Enables operation TRMD11 0 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 4 Note 5 1 SSE11 Note 2 Receive mode (transmission disabled).
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-3.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (3) Port mode registers 0 and 3 (PM0, PM3) These registers set input/output of ports 0 and 3 in 1-bit units. When using P35/SCK11 as the clock output pin of the serial interface, clear PM35 to 0, and set the output latches of P35 to 1. When using P37/SO11 as the data output pin of the serial interface, clear PM37 and the output latches of P37 to 0.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 16.4 Operation of Serial Interface CSI11 Serial interface CSI11 can be used in the following two modes.  Operation stop mode  3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the SCK11, SI11, SO11, and SSI11 pins can be used as ordinary I/O port pins in this mode.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK11), serial output (SO11), and serial input (SI11) lines.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 The relationship between the register settings and pins is shown below. Table 16-2.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD11) of serial operation mode register 11 (CSIM11) is 1. Transmission/reception is started when a value is written to transmit buffer register 11 (SOTB11).
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-6. Timing in 3-Wire Serial I/O Mode (1/2) Note (a) Transmission/reception timing (Type 1: TRMD11 = 1, DIR11 = 0, CKP11 = 0, DAP11 = 0, SSE11 = 1 ) SSI11Note SCK11 Read/write trigger SOTB11 SIO11 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT11 INTCSI11 CSIIF11 SI11 (receive AAH) SO11 55H is written to SOTB11. Note The SSE11 flag and SSI11 pins are used in the slave mode. R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-6. Timing in 3-Wire Serial I/O Mode (2/2) Note (b) Transmission/reception timing (Type 2: TRMD11 = 1, DIR11 = 0, CKP11 = 0, DAP11 = 1, SSE11 = 1 ) SSI11Note SCK11 Read/write trigger SOTB11 SIO11 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT11 INTCSI11 CSIIF11 SI11 (input AAH) SO11 55H is written to SOTB11. Note The SSE11 flag and SSI11 pins are used in the slave mode. R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-7.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (3) Timing of output to SO11 pin (first bit) When communication is started, the value of transmit buffer register 11 (SOTB11) is output from the SO11 pin. The output operation of the first bit at this time is described below. Figure 16-8.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-8.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (4) Output value of SO11 pin (last bit) After communication has been completed, the SO11 pin holds the output value of the last bit. Figure 16-9. Output Value of SO11 Pin (Last Bit) (1/2) (a) Type 1: CKP11 = 0, DAP11 = 0 SCK11 ( ← Next request is issued.) Writing to SOTB11 or reading from SIO11 SOTB11 SIO11 Output latch SO11 Last bit (b) Type 3: CKP11 = 1, DAP11 = 0 SCK11 Writing to SOTB11 or reading from SIO11 ( ← Next request is issued.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 Figure 16-9. Output Value of SO11 Pin (Last Bit) (2/2) (c) Type 2: CKP11 = 0, DAP11 = 1 SCK11 Writing to SOTB11 or reading from SIO11 ( ← Next request is issued.) SOTB11 SIO11 Output latch SO11 Last bit (d) Type 4: CKP11 = 1, DAP11 = 1 SCK11 Writing to SOTB11 or reading from SIO11 ( ← Next request is issued.) SOTB11 SIO11 Output latch SO11 R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 16 SERIAL INTERFACE CSI11 (5) SO11 output (refer to Figure 16-1) The status of the SO11 output is as follows depending on the setting of CSIE11, TRMD11, DAP11, and DIR11. Table 16-3. SO11 Output Status CSIE11 CSIE11 = 0 Note 2 TRMD11 TRMD11 = 0 Note 2 TRMD11 = 1 Note 3 DAP11 DIR11   Low level output  Low level output DAP11 = 0 DAP11 = 1 DIR11 = 0 DIR11 = 1 CSIE11 = 1 Notes 1.
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78K0/Ix2 CHAPTER 17 MULTIPLIER CHAPTER 17 MULTIPLIER 17.1 Functions of Multiplier The multiplier is mounted onto all 78K0/Ix2 microcontroller products. The multiplier has the following functions.  Can execute calculation of 8 bits  8 bits = 16 bits.  Can execute calculation of 16 bits  16 bits = 32 bits. Figure 17-1 shows the block diagram of the multiplier. Figure 17-1.
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78K0/Ix2 CHAPTER 17 MULTIPLIER 17.2 Configuration of Multiplier (1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage register (MUL0H, MUL0L) These two registers, MUL0H and MUL0L, are used to store a 32-bit multiplication result. In the case of multiplication of 8 bits by 8 bits, the 16 bits of the multiplication result are stored in MUL0L.
PAGE 582
78K0/Ix2 CHAPTER 17 MULTIPLIER (2) Multiplication input data registers A, B (MULA, MULB) These are 16-bit registers that store data for multiplication. The multiplier multiplies the values of MULA and MULB. MULA and MULB can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears these registers to 0000H. Caution In the case of multiplication of 8 bits by 8 bits, set the multiplied data to MULAL and MULBL. Figure 17-3.
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78K0/Ix2 CHAPTER 17 MULTIPLIER 17.3 Operation of Multiplier The result of the multiplication can be obtained by storing the values in the MULA and MULB registers and then reading the MUL0H and MUL0L registers after waiting for 1 clock. The result can also be obtained after 1 clock or more has elapsed, even when fixing either of MULA or MULB and rewrite the other of these. The result can be read without problem, regardless of whether MUL0H or MUL0L is read in first.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS CHAPTER 18 INTERRUPT FUNCTIONS Item Maskable interrupts 78K0/IY2 78K0/IA2 16 pins 20 pins 78K0/IB2 30 pins 32 pins External 7 7 9 8 internal 8 12 13 13 18.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Table 18-1.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Table 18-1. Interrupt Source List (2/2) Interrupt Internal/ Type Basic Default External Configuration Priority Type Note 1 2 Note Vector Table Interrupt Source Name Address Trigger IY2 IA2 IB2 16 20 30 32 pins pins pins pins Software  (C)  BRK BRK instruction execution 003EH     Reset    RESET Reset input 0000H     POC Power-on clear LVI Low-voltage detection WDT WDT overflow Notes 1. 2.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-1.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt request R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS 18.3 Registers Controlling Interrupt Functions The following 7 types of registers are used to control the interrupt functions.
PAGE 590
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-2.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-3.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-4.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 18-5.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-6.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-7.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-9.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-10.
PAGE 600
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (4) Port alternate switch control register (MUXSEL) This register assigns the pin function. The interrupt input (INTP0) function can be assigned to the P121 or P125 pin of the 78K0/IY2 and the P121 pin of the 78K0/IA2 and 78K0/IB2. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 18-11.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (5) External interrupt rising edge enable registers 0, 1 (EGPCTL0, EGPCTL1) , external interrupt falling edge enable registers 0, 1 (EGNCTL0, EGNCTL1) EGPCTL0, EGPCTL1, EGNCTL0, and EGNCTL1 are the registers that set the INTPm and INTCMP0 to INTCMP2 valid edges. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
PAGE 602
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-12.
PAGE 603
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Table 18-3 shows the ports corresponding to EGPn and EGNn. Table 18-3.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Table 18-3.
PAGE 605
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI).
PAGE 606
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS 18.4 Interrupt Servicing Operations 18.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-14.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-15. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 18-16.
PAGE 609
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS 18.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-17. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-17. Examples of Multiple Interrupt Servicing (2/2) Example 3.
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78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS 18.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.  MOV PSW, #byte  MOV A, PSW  MOV PSW, A  MOV1 PSW. bit, CY  MOV1 CY, PSW. bit  AND1 CY, PSW. bit  OR1 CY, PSW. bit  XOR1 CY, PSW.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function is mounted onto all 78K0/Ix2 microcontroller products. The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION 19.1.2 Registers controlling standby function The standby function is controlled by the following two registers.  Oscillation stabilization time counter status register (OSTC)  Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, refer to CHAPTER 5 CLOCK GENERATOR.
PAGE 615
78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 11 204.8 s min. 13 819.2 s min. 14 1.64 ms min. 15 3.27 ms min. 16 6.55 ms min. 1 0 0 0 0 2 /fX min. 1 1 0 0 0 2 /fX min.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Figure 19-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 0 1 1 0 1 1 1.64 ms 15 3.27 ms 16 6.55 ms 2 /fX 0 0 819.2 s 14 2 /fX 1 0 204.8 s 13 2 /fX 0 1 11 2 /fX 1 2 /fX Other than above Setting prohibited Cautions 1.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Table 19-1.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-3.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Table 19-2. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt MK PR IE ISP 0 0 0  request Operation Next address instruction execution 0 0 1  Interrupt servicing execution 0 1 0 1 Next address 0 1  0 instruction execution 0 1 1 1 Interrupt servicing execution Reset 1    HALT mode held     Reset processing : don’t care 19.2.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Table 19-3.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. When transitioning to the STOP mode, it is possible to achieve low power consumption by setting RMC = 56H. 3.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION (2) STOP mode release Figure 19-5.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Figure 19-6.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Figure 19-6.
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78K0/Ix2 CHAPTER 19 STANDBY FUNCTION Figure 19-7.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION CHAPTER 20 RESET FUNCTION The reset function is mounted onto all 78K0/Ix2 microcontroller products. The following four operations are available to generate a reset signal.
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R01UH0010EJ0500 Rev.5.00 Feb 28, 2012 Set Clear 2. LVIS: Low-voltage detection level selection register Remarks 1. LVIM: Low-voltage detection register Caution An LVI circuit internal reset does not reset the LVI circuit. Low-voltage detector reset signal Power-on-clear circuit reset signal RESET RESF register read signal Watchdog timer reset signal WDTRF Clear Set LVIRF Reset control flag register (RESF) Internal bus Figure 20-1.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Figure 20-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (102 to 407 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Figure 20-4. Timing of Reset in STOP Mode by RESET Input STOP instruction execution Wait for oscillation accuracy stabilization (102 to 407 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Table 20-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock fIH Operation stopped fX Operation stopped (X1 and X2 pins are input port mode) fEXCLK Clock input invalid (EXCLK pin is input port mode) fIL Operation stopped CPU Flash memory Operation stopped (The value, however, is retained when the voltage is at least the power-on RAM clear detection voltage.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Table 20-2. Hardware Statuses After Reset Acknowledgment (1/4) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set.
PAGE 633
78K0/Ix2 CHAPTER 20 RESET FUNCTION Table 20-2.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Table 20-2.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION Table 20-2.
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78K0/Ix2 CHAPTER 20 RESET FUNCTION 20.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/Ix2 microcontrollers. The reset control flag register (RESF is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 20-5.
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) is mounted onto all 78K0/Ix2 microcontroller products. The power-on-clear circuit has the following functions.  Generates internal reset signal at power on.  The reset signal is released when the supply voltage (VDD) exceeds POC detection voltage (VPOR = 1.61 V 0.09 V).
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal − Reference voltage source 21.3 Operation of Power-on-Clear Circuit  An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds POC detection voltage (VPOR = 1.61 V 0.09 V), the reset status is released.
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) When LVI is OFF upon power application (option byte: LVISTART = 0) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Supply voltage (VDD) VLVI 2.7 VNote 1 VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.) 0.5 V/ms (MIN.
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) When LVI is ON upon power application (option byte: LVISTART = 1) Set LVI to be used for interrupt Set LVI to be used for reset Set LVI to be used for reset Supply voltage (VDD) VLVI 2.7 VNote 1 VLVI = 1.91 V (TYP.) VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
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78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Reset Release (2/2)  Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated R01UH0010EJ0500 Rev.5.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) is mounted onto all 78K0/Ix2 microcontroller products. The low-voltage detector has the following functions.  The LVI circuit compares the supply voltage (VDD) with the LVI detection voltage (VLVI), and generates an internal reset or internal interrupt signal.  The low-voltage detector (LVI) can be set to ON by an option byte by default.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 22-1. Figure 22-1. Block Diagram of Low-Voltage Detector VDD VDD Internal reset signal Selector Low-voltage detection level selector N-ch + − INTLVI Reference voltage source 4 LVION LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) LVIF Low-voltage detection register (LVIM) Internal bus 22.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-2.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. Figure 22-3.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1) Compares the supply voltage (VDD) and LVI detection voltage (VLVI), generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD  VLVI. Remark The low-voltage detector (LVI) can be set to ON by an option byte by default.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.1 When used as reset (1) When LVI default start function stopped is set (LVISTART = 0)  When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MAX.)).
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-4. Timing of Low-Voltage Detector Internal Reset Signal Generation (LVISTART = 0) Set LVI to be used for reset Supply voltage (VDD) VLVI VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as described in 22.4.1 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (LVISTART = 1) Set LVI to be used for reset Supply voltage (VDD) VLVI VLVI = 1.91 V (TYP.) VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.2 When used as interrupt (1) When LVI default start function stopped is set (LVISTART = 0)  When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Timing of Low-Voltage Detector Interrupt Signal Generation (LVISTART = 0) Supply voltage (VDD) VLVI VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.) Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 <8> Cleared by software <2> LVION flag (set by software) <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag Note 2 <7> Cleared by software LVIMD flag (set by software) L <3> Internal reset signal Notes 1.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as described in 22.4.2 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (LVISTART = 1) Supply voltage (VDD) VLVI VLVI = 1.91 V (TYP.) VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. Operation example 1: When used as reset The system may be repeatedly reset and released from the reset status.
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8. Example of Software Processing After Reset Release (1/2)  If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check the reset sourceNote Initialization processing <1> LVI reset ; Setting of detection level by LVIS. The low-voltage detector operates (LVION = 1).
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78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8. Example of Software Processing After Reset Release (2/2)  Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector Operation example 2: When used as interrupt Interrupt requests may be generated frequently. Take the following action.
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78K0/Ix2 CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The 78K0/Ix2 microcontrollers contain a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 F). However, when using the STOP mode that has been entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 F is recommended.
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78K0/Ix2 CHAPTER 23 REGULATOR 23.3 Cautions for Self Programming 1. Make sure that the regulator output voltage mode is fixed when executing self programming or EEPROM emulation. 2. Program area can be rewritten by using the self programming library in normal power mode. 3. Observe the following points when rewriting the flash memory in low power consumption mode: • Data area can be rewritten in low power consumption mode, but program area cannot.
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78K0/Ix2 CHAPTER 24 OPTION BYTE CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/Ix2 microcontrollers is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes.
PAGE 660
78K0/Ix2 CHAPTER 24 OPTION BYTE (3) 0082H/1082H  Internal high-speed oscillation clock frequency selection  4 MHz (TYP.)  8 MHz (TYP.) Caution Set a value that is the same as that of 0082H to 1082H because 0082H and 1082H are switched during the boot swap operation.
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78K0/Ix2 CHAPTER 24 OPTION BYTE Figure 24-1.
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78K0/Ix2 CHAPTER 24 OPTION BYTE Figure 24-1. Format of Option Byte (2/3) Address: 0081H/1081H Notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LVISTART LVISTART Notes 1. LVI default start operation control 0 LVI is OFF by default upon power application (LVI default start function stopped) 1 LVI is ON by default upon power application (LVI default start function enabled) LVISTART can only be written by using a dedicated flash memory programmer.
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78K0/Ix2 CHAPTER 24 OPTION BYTE Figure 24-1. Format of Option Byte (3/3) Address: 0083H/1083H Note 7 6 5 4 3 2 1 0 0 0 0 1 1 1 OCDPSEL 0 OCDPSEL Pin selection used during on-chip debugging 0 TOOLC1/P31, TOOLD1/P32 1 TOOLC0/X1, TOOLD0/X2 Note Set a value that is the same as that of 0083H to 1083H because 0083H and 1083H are switched during the boot swap operation. Caution Be sure to clear bits 7 to 5 and 0 to “0” and set bits 4 to 2 to “1”.
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78K0/Ix2 CHAPTER 24 OPTION BYTE Here is an example of description of the software for setting the option bytes. OPT CSEG OPTION: DB AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 27/fIL, ; Internal low-speed oscillator can be stopped by software. DB 00H ; LVI default start function stopped DB 01H ; Internal high-speed oscillation clock frequency 4 MHz (TYP.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY CHAPTER 25 FLASH MEMORY The 78K0/Ix2 microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 25.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Table 25-1. Set Values of Internal Memory Size Switching Register Products 78K0/IY2 IMS Setting 78K0/IA2 78K0/IB2   PD78F0740, 61H 78F0750 PD78F0741, PD78F0743, PD78F0745, 78F0751 78F0753 78F0755 PD78F0742, PD78F0744, PD78F0746, 78F0752 78F0754 78F0756 42H 04H 25.2 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/Ix2 microcontrollers are illustrated below. Figure 25-2.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.4 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.4.2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.4.7 On-board writing when connecting crystal/ceramic resonator To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.5 Programming Method 25.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Manipulate flash memory End? No Yes End 25.5.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/Ix2 microcontrollers in the flash memory programming mode.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Table 25-5. Flash Memory Control Commands Classification Verify Command Name Function Compares the contents of a specified area of the flash memory with Verify data transmitted from the programmer. Erase Blank check Chip Erase Erases the entire flash memory. Block Erase Erases a specified area in the flash memory. Block Blank Check Checks if a specified block in the flash memory has been correctly erased.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.6 Security Settings The 78K0/Ix2 microcontrollers support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Table 25-7. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Prohibition of batch erase (chip erase) Prohibition of block erase Block Erase Write Note Cannot be erased in batch Blocks cannot be Can be performed Can be erased in batch. erased. Can be performed. Prohibition of writing . Cannot be performed.
PAGE 675
78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.7 Processing Time for Each Command When PG-FP5 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP5 is used as a dedicated flash memory programmer. Table 25-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (1/2) (1) Products with internal ROMs of the 4 KB: PD78F0740, 78F0750 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (fIH: 8 MHz (typ.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Table 25-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (2/2) (3) Products with internal ROMs of the 16 KB: PD78F0742, 78F0744, 78F0746, 78F0752, 78F0754, 78F0756 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (fIH: 8 MHz (typ.)), Speed: 500,000 bps Signature 0.5 s (typ.) Blankcheck 0.5 s (typ.) Erase 1 s (typ.) Program 2.5 s (typ.) Verify 1.5 s (typ.) E.P.V 2.5 s (typ.) Checksum 1 s (typ.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.8 Flash Memory Programming by Self-Programming The 78K0/Ix2 microcontrollers support a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Ix2 microcontroller self-programming library, it can be used to upgrade the program in the field.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.8.1 Register controlling self programming mode The self programming mode is controlled by the self programming mode control register (FPCTL). FPCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears FPCTL to 00H. Figure 25-8.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Figure 25-9.
PAGE 680
78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.8.3 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY Figure 25-11.
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78K0/Ix2 CHAPTER 25 FLASH MEMORY 25.9 Creating ROM Code to Place Order for Previously Written Product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). The HCU is a software tool that includes functions required for creating ROM code.
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78K0/Ix2 CHAPTER 26 ON-CHIP DEBUG FUNCTION CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.1 Connecting QB-MINI2 to 78K0/Ix2 Microcontrollers The 78K0/Ix2 microcontrollers use the VDD, RESET, TOOLC0/X1 (or TOOLC1/P31), TOOLD0/X2 (or TOOLD1/P32), and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). Whether TOOLC0/X1 and TOOLC1/P31, or TOOLD0/X2 and TOOLD1/P32 are used can be selected. Cautions 1.
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78K0/Ix2 CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (1/3) (1) When using the TOOLC0 and TOOLD0 pins (X1 oscillator or EXCLK input clock is not used, both debugging and programming are performed) VDD Target connector GND RESET_OUT RxD VDD TxD R.F.U. R.F.U. R.F.U. CLKNote 2 R.F.U. R.F.U. FLMD1 DATA FLMD0 Note 5 RESET_IN R.F.U.
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78K0/Ix2 CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (2/3) (2) When using the TOOLC0 and TOOLD0 pins (with X1/X2 oscillator is used, both debugging and programming are performed) VDD Target connector GND RESET_OUT RxD VDD TxD R.F.U. R.F.U. R.F.U. CLK Note 2 R.F.U. R.F.U. FLMD1 DATA FLMD0 Note 4 RESET_IN R.F.U.
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78K0/Ix2 CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (3/3) (3) When using the TOOLC1 and TOOLD1 pins (both debugging and programming are performed) VDD Target connector GND RESET_OUT RxD VDD TxD R.F.U. R.F.U. R.F.U. CLKNote 2 R.F.U. R.F.U. FLMD1 DATA FLMD0 Note 5 RESET_IN R.F.U.
PAGE 687
78K0/Ix2 CHAPTER 26 ON-CHIP DEBUG FUNCTION Table 26-1. On-Chip Debug Security ID Address On-Chip Debug Security ID 0085H to 008EH Any ID code of 10 bytes 1085H to 108EH 26.3 Securing of User Resources QB-MINI2 uses the user memory spaces (shaded portions in Figure 26-2) to implement communication with the target device, or each debug functions. The areas marked with a dot (•) are always used for debugging, and other areas are used for each debug function used.
PAGE 688
78K0/Ix2 CHAPTER 27 INSTRUCTION SET CHAPTER 27 INSTRUCTION SET This chapter lists each instruction set of the 78K0/Ix2 microcontrollers in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 27.1 Conventions Used in Operation List 27.1.
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78K0/Ix2 CHAPTER 27 INSTRUCTION SET 27.1.
PAGE 690
78K0/Ix2 CHAPTER 27 INSTRUCTION SET 27.
PAGE 691
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group 16-bit data Mnemonic MOVW transfer Operands Bytes Note 1 Note 2 3 6  rp  word saddrp, #word 4 8 10 (saddrp)  word sfrp, #word 4  10 sfrp  word AX, saddrp 2 6 8 AX  (saddrp) saddrp, AX 2 6 8 (saddrp)  AX AX, sfrp 2  8 AX  sfrp 2  8 sfrp  AX AX, rp Note 3 1 4  AX  rp rp, AX Note 3 1 4  rp  AX AX, !addr16 3 10 12 AX  (addr16) !addr16, AX 3 10 12 (addr16)  AX 1 4  AX  rp N
PAGE 692
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group 8-bit Mnemonic SUB operation Operands Bytes Note 2 4  A, CY  A  byte    3 6 8 (saddr), CY  (saddr)  byte    2 4  A, CY  A  r    r, A 2 4  r, CY  r  A    A, saddr 2 4 5 A, CY  A  (saddr)    A, !addr16 3 8 9 A, CY  A  (addr16)    A, [HL] 1 4 5 A, CY  A  (HL)    Note 3 A, [HL + byte] 2 8 9 A, CY  A  (HL + byte)    A, [HL + B] 2 8 9 A, CY  A 
PAGE 693
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group 8-bit Mnemonic OR Operands Bytes Note 2 4  A  A  byte 3 6 8 (saddr)  (saddr)  byte  2 4  AAr  r, A 2 4  rrA  A, saddr 2 4 5 A  A  (saddr)  A, !addr16 3 8 9 A  A  (addr16)  A, [HL] 1 4 5 A  A  (HL)  A, r Note 3 2 8 9 A  A  (HL + byte)  A, [HL + B] 2 8 9 A  A  (HL + B)  A, [HL + C] 2 8 9 A  A  (HL + C)  A, #byte 2 4  A  A  byte  3 6 8 (saddr)  (sadd
PAGE 694
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Bytes Clocks Operation Flag Z AC CY Note 1 Note 2 16-bit ADDW AX, #word 3 6  AX, CY  AX + word    operation SUBW AX, #word 3 6  AX, CY  AX  word    CMPW AX, #word 3 6  AX  word     AX  A  X Multiply/ MULU X 2 16 divide DIVUW C 2 25  AX (Quotient), C (Remainder)  AX  C Increment/ INC r 1 2  rr+1   saddr 2 4 6 (saddr)  (saddr) + 1   decremen
PAGE 695
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group Bit Mnemonic AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Operands Bytes Clocks Operation Flag Z AC CY Note 1 Note 2 6 7 CY  CY  (saddr.bit)  3  7 CY  CY  sfr.bit  2 4  CY  CY  A.bit  3  7 CY  CY  PSW.bit  CY, saddr.bit 3 CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit 2 6 7 CY  CY  (HL).bit  CY, saddr.bit 3 6 7 CY  CY  (saddr.bit)  CY, sfr.bit 3  7 CY  CY  sfr.bit  CY, A.
PAGE 696
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group Call/return Mnemonic CALL Operands !addr16 Bytes 3 Clocks Note 1 Note 2 7  Operation Flag Z AC CY (SP  1)  (PC + 3)H, (SP  2)  (PC + 3)L, PC  addr16, SP  SP  2 CALLF !addr11 2 5  (SP  1)  (PC + 2)H, (SP  2)  (PC + 2)L, PC15  11  00001, PC10  0  addr11, SP  SP  2 CALLT [addr5] 1 6  (SP  1)  (PC + 1)H, (SP  2)  (PC + 1)L, PCH  (addr5 + 1), PCL  (addr5), SP  SP  2 BRK 1 6  (SP  1)  PSW, (SP  2) 
PAGE 697
78K0/Ix2 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Operation Note 2 8 9 4  11 PC  PC + 4 + jdisp8 if sfr.bit = 1 3 8  PC  PC + 3 + jdisp8 if A.bit = 1 3  9 PC  PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC  PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC  PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4  11 PC  PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8  PC  PC + 3 + jdisp8 if A.bit = 0 PSW.
PAGE 698
78K0/Ix2 CHAPTER 27 INSTRUCTION SET 27.
PAGE 699
78K0/Ix2 CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW saddrp MOVW !addr16 SP MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.
PAGE 700
78K0/Ix2 CHAPTER 27 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP R01UH0010EJ0500 Rev.5.
PAGE 701
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS CHAPTER 28 ELECTRICAL SPECIFICATIONS Target products: 78K0/IY2: PD78F0740, 78F0741, 78F0742, 78F0750, 78F0751, 78F0752 78K0/IA2: PD78F0743, 78F0744, 78F0753, 78F0754 78K0/IB2: PD78F0745, 78F0746, 78F0755, 78F0756 Cautions 1. The 78K0/Ix2 Microcontrollers have an on-chip debug function, which is provided for development and evaluation.
PAGE 702
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) Non-port functions Port Power supply, 78K0/IY2 78K0/IA2 16 pins 20 pins VDD, VSS, AVREF 78K0/IB2 30 pins 32 pins VDD, AVREF, VSS, AVSS ground Regulator REGC Reset RESET Clock X1, X2, EXCLK oscillation Interrupt INTP0, INTP2 to INTP4 TMX0, INTP0 to INTP5 INTP0, INTP2 to INTP5 TI000, TI010, TO00 TI000 TOX00, TOX01, TOX10, TOX11 Serial interface Timer TMX1 TM00 TI000 TM51 TI51 TMH1 TOH1 UART6/  RxD6, TxD6  SCLA0, SDAA0 D
PAGE 703
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Symbol Supply voltage Conditions Ratings Unit VDD 0.5 to +6.5 V VSS 0.5 to +0.3 0.5 to VDD + 0.3 AVREF REGC pin input voltage Input voltage Note 2 V Note 1 AVSS 0.5 to +0.3 VIREGC –0.5 to +3.6 and –0.
PAGE 704
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbol IOH1 Conditions Per pin P00 to P02, P30 to P37, Ratings Unit 10 mA P60, P61 Total of all pins P00 to P02 40 mA P30 to P37, P60, P61 15 mA 25 mA Per pin 0.
PAGE 705
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.2 Oscillator Characteristics 28.2.1 X1 Oscillator Characteristics (TA = 40 to +105C, 2.7 V  VDD  5.5 V, VSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic/ Conditions X1 clock VSS X1 crystal Parameter X2 MIN. TYP. 1.0 MAX. Unit 10.0 MHz oscillation Note 1 resonator frequency (fX) C1 C2 Multiplied X1 40.
PAGE 706
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.2.2 Internal High-speed Oscillator Characteristics (TA = 40 to +105C, 2.7 V  VDD  5.
PAGE 707
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.3 DC Characteristics 28.3.1 Pin Characteristics (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Parameter Symbol Output current, high Note 1 IOH1 Conditions MAX. Unit 4.0 V  VDD  5.5 V 3.0 mA P37, P60, P61 2.7 V  VDD < 4.0 V 2.5 mA Total of P00 to P02 4.0 V  VDD  5.5 V 4.5 mA 2.7 V  VDD < 4.
PAGE 708
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Parameter Input voltage, high Symbol Output voltage, high MIN. TYP. MAX. Unit 0.7VDD VDD V 0.7AVREF AVREF V VIH1 P37, P121, P122, P125 VIH2 P20 to P27, P70 VIH3 P60, P61 (I/O port mode) 0.7VDD VDD V VIH4 P00 to P02, P30 to P36, RESET, EXCLK 0.
PAGE 709
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 Conditions P00 to P02, P30 to P37 MIN. TYP. MAX. Unit 0.7 V 0.7 V 0.4 V 2.0 V 0.4 V 0.6 V 0.4 V VI = VDD 3 A 4.0 V  VDD  5.5 V, IOL1 = 8.5 mA 2.7 V  VDD < 4.0 V, IOL1 = 5.
PAGE 710
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.3.2 Supply current Characteristics (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Parameter Supply current 1 Symbol Note Note 2 IDD1 Conditions Operating mode MIN. TYP. MAX. Unit 1.6 3.7 mA fXH = 10 MHz, VDD = 5.0 V, RMC = 00H Square wave input Resonator connection 2.3 5.1 mA fXH = 10 MHz, VDD = 3.
PAGE 711
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Parameter Symbol Watchdog timer operating current IWDT VDD = 5.0 V Note 1 TMH1 operating current Conditions TYP. MAX. Unit 0.28 0.35 A 0.35 2 A 9 18 A AVREF = VDD = 5.0 V 1.72 3.2 mA AVREF = VDD = 3.0 V 0.72 1.6 mA AVREF = VDD = 5.0 V 0.86 1.9 mA 1.
PAGE 712
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.4 AC Characteristics 28.4.1 Basic operation (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions Main In normal power mode (RMC = 0.2 system 00H) 0.1 clock (fXP) operation Peripheral hardware clock fPRS frequency MIN.
PAGE 713
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation, RMC = 00H (Normal Power Mode)) 100 32 10 Cycle time TCY [ μ s] 5.0 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] Caution The following operations and register settings can be performed in the shaded area in the figure (1.8 V  VDD < 2.
PAGE 714
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation, RMC = 56H (Low Power Consumption Mode)) 100 32 10 5.0 Cycle time TCY [ μ s] Guaranteed operation range 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 5.0 5.5 6.0 4.0 2.
PAGE 715
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TI Timing tTIH0 tTIL0 TI000, TI010 1/fTI5 tTIL5 tTIH5 tINTL tINTH TI51 Interrupt Request Input Timing INTP0 to INTP5 RESET Input Timing tRSL RESET R01UH0010EJ0500 Rev.5.
PAGE 716
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.4.2 Serial interface (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V) (a) UART6/DALI (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 625 kbps (b) IICA Parameter Symbol SCLA0 clock frequency fSCL Conditions Fast mode: fPRS  3.
PAGE 717
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (c) CSI11 (master mode, SCK11... internal clock output) Parameter SCK11 cycle time SCK11 high-/low-level width Symbol Conditions tKCY1 MIN. TYP. MAX. 200 tKCY1/2  10 tKH1, Unit ns Note 1 ns tKL1 SI11 setup time (to SCK11) tSIK1 SI11 hold time (from SCK11) tKSI1 Delay time from SCK11 to tKSO1 30 ns 30 ns Note 2 C = 50 pF 40 ns MAX.
PAGE 718
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing IICA: tLOW tR SCLA0 tHD: DAT tHIGH tF tSU: STA tHD: STA tSU: STO tSU: DAT tHD: STA SDAA0 tBUF Stop condition Start condition Restart condition Stop condition CSI11: tKCY1 tKL1 tKH1 SCK11 tSIK1 SI11 tKSI1 Input data tKSO1 SO11 R01UH0010EJ0500 Rev.5.
PAGE 719
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5 Analog Characteristics 28.5.1 A/D Converter Characteristics (TA = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V) Parameter Symbol Resolution MIN.
PAGE 720
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.2 Internal voltage (1.2 V) generator for analog input of A/D converter (TA = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V) Parameter Symbol Output voltage range Operation stabilization wait time Conditions VOFO Note MIN. TYP. MAX. 1.14 1.18 1.
PAGE 721
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.4 Operational amplifier (TA = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V, Output load: RL = 47 k, CL = 50 pF) Parameter Symbol Conditions Input offset voltage VIOP VBIAS = 1/2 VDD, AVREF = 3.0 V Output voltage, high VOHOP0 AVREF = 3.0 V/2.2 V, IOH =  500 A Output voltage, low VOLOP0 AVREF = 3.0 V/2.
PAGE 722
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.5 Comparator (TA = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V) Parameter Symbol Input offset voltage VIOCMP Input voltage range VICMP Conditions tCR, tCF Operation stabilization wait time Note TYP. 5 CMP0+, CMP1+, CMP2+ CMPCOM Response time MIN. MAX. Unit 40 mV 0 AVREF V 0.045 0.
PAGE 723
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (TA = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CnVRS4 CnVRS3 CnVRS2 CnVRS1 CnVRS0 Internal reference VIREF0 0 0 0 0 0 0.00 0.05 0.11 V voltage VIREF1 0 0 0 0 1 0.04 0.10 0.16 V VIREF2 0 0 0 1 0 0.09 0.15 0.21 V VIREF3 0 0 0 1 1 0.14 0.20 0.
PAGE 724
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.6 POC (TA = 40 to +105C, VSS = 0 V) Parameter Symbol Detection voltage Power supply voltage rise Conditions MIN. TYP. MAX. Unit VPOR 1.52 1.61 1.70 V VPDR 1.50 1.59 1.68 V tPTH Change inclination of VDD: 0 V  VPOR 0.
PAGE 725
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.7 Supply Voltage Rise Time (TA = 40 to +105C, VSS = 0 V) Parameter Maximum time to rise to 2.7 V (VDD (MIN.)) Symbol Note tPUP1 (VDD: 0 V  2.7 V) Conditions MIN. TYP. LVI default start function stopped is MAX. Unit 5.4 ms 1.9 ms set (LVISTART (Option Byte) = 0), when RESET input is not used Maximum time to rise to 2.7 V (VDD (MIN.
PAGE 726
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 28.5.8 LVI (TA = 40 to +105C, VPDR  VDD  5.5 V, AVREF  VDD, VSS =0 V) Parameter Detection Symbol Supply voltage level voltage Conditions MIN. TYP. MAX. Unit VLVI0 4.12 4.22 4.32 V VLVI1 3.97 4.07 4.17 V VLVI2 3.82 3.92 4.02 V VLVI3 3.66 3.76 3.86 V VLVI4 3.51 3.61 3.71 V VLVI5 3.35 3.45 3.55 V VLVI6 3.20 3.30 3.
PAGE 727
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = 40 to +105C) Parameter Data retention supply voltage Symbol Conditions MIN. Note VDDDR 1.50 TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage.
PAGE 728
78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.6 Flash Memory Programming Characteristics (TA = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V)  Basic characteristics Parameter Symbol Conditions MIN. VDD supply current IDD Number of Cerwr rewrites per chip 1 erase + In When a flash Retention: 1 write after normal memory 15 years erase = Note 1 rewrite power programmer is mode used, and the self- (RMC = programming 00H) libraries provided 1 TYP. MAX.
PAGE 729
78K0/Ix2 CHAPTER 29 PACKAGE DRAWINGS CHAPTER 29 PACKAGE DRAWINGS 29.1 78K0/IY2  PD78F0740MA-FAA-AX, 78F0741MA-FAA-AX, 78F0742MA-FAA-AX, 78F0750MA-FAA-AX, 78F0751MA-FAA-AX, 78F0752MA-FAA-AX 16-PIN PLASTIC SSOP (4.4x5.0) D1 D detail of lead end 9 16 A3 E 1 c 8 L Lp ZD bp x M S HE A A2 L1 S A1 y S S e (UNIT:mm) ITEM D 5.00 ± 0.15 D1 5.20 ± 0.15 E 4.40 ± 0.20 HE 6.40 ± 0.20 A 1.725 MAX. A1 0.125 ± 0.05 A2 1.50 A3 0.25 e 0.65 bp 0.22 + 0.08 0.07 c 0.15 + 0.03 0.
PAGE 730
78K0/Ix2 CHAPTER 29 PACKAGE DRAWINGS 29.2 78K0/IA2  PD78F0743MC-CAA-AX, 78F0744MC-CAA-AX, 78F0753MC-CAA-AX, 78F0754MC-CAA-AX 20-PIN PLASTIC SSOP (7.62 mm (300)) V 11 20 detail of lead end T I P L 10 1 U V W A W H F G J S C E D N M M K S (UNIT:mm) B ITEM A B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 6.50±0.10 0.325 C 0.65 (T.P.) D 0.22 +0.10 −0.05 E 0.10±0.05 F 1.30±0.10 G 1.20 H 8.10±0.20 I 6.
PAGE 731
78K0/Ix2 CHAPTER 29 PACKAGE DRAWINGS  PD78F0743MC-GAB-AX, 78F0744MC-GAB-AX, 78F0753MC-GAB-AX, 78F0754MC-GAB-AX θ ± ± ± + − ± ± + − ± ± θ R01UH0010EJ0500 Rev.5.
PAGE 732
78K0/Ix2 CHAPTER 29 PACKAGE DRAWINGS 29.3 78K0/IB2  PD78F0745MC-CAB-AX, 78F0746MC-CAB-AX, 78F0755MC-CAB-AX, 78F0756MC-CAB-AX 30-PIN PLASTIC SSOP (7.62mm (300)) 30 V 16 detail of lead end T I P 1 U V 15 W L W A H F G J S C E D N S B M M K (UNIT:mm) ITEM A B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 9.70±0.10 0.30 C 0.65 (T.P.) D 0.22 +0.10 −0.05 E 0.10±0.05 F 1.30±0.10 G 1.20 H 8.10±0.20 I 6.10±0.
PAGE 733
78K0/Ix2 CHAPTER 29 PACKAGE DRAWINGS  PD78F0745K8-3B4-AX, 78F0746K8-3B4-AX, 78F0755K8-3B4-AX, 78F0756K8-3B4-AX ± ± ± ± ± + ± R01UH0010EJ0500 Rev.5.
PAGE 734
78K0/Ix2 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact a Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Package Mount Manual (http://www.renesas.com/products/package/manual/index.jsp) Table 30-1.
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78K0/Ix2 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS Table 30-1. Surface Mounting Type Soldering Conditions (2/2) (2) 32-pin plastic WQFN (fine pitch) (5 x 5) PD78F0745K8-3B4-AX, 78F0746K8-3B4-AX, 78F0755K8-3B4-AX, 78F0756K8-3B4-AX Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max.
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78K0/Ix2 CHAPTER 31 CAUTIONS FOR WAIT CHAPTER 31 CAUTIONS FOR WAIT 31.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
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78K0/Ix2 CHAPTER 31 CAUTIONS FOR WAIT Table 31-1.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/Ix2 microcontrollers. Figure A-1 shows the development tool configuration. R01UH0010EJ0500 Rev.5.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS Figure A-1.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS Figure A-1.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K0 microcontrollers are combined in this 78K0 microcontroller software package. package A.2 Language Processing Software RA78K0 Note 1 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Programming Tools A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 PG-FP5, FL-PR5 Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Flash memory programmer FA-xxxx Note Flash memory programming adapter used connected to the flash memory programmer Flash memory programming adapter Note for use.
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78K0/Ix2 APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0IX2 In-circuit emulator This in-circuit emulator serves to debug hardware and software when developing application systems using the 78K0/Ix2 microcontrollers. It supports to the integrated debugger (ID78K0QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. A.4.
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78K0/Ix2 APPENDIX B REGISTER INDEX APPENDIX B REGISTER INDEX [A] ADCR: 10-bit A/D conversion result register ...................................................................................................... 372 ADCRH: 8-bit A/D conversion result register H..................................................................................................... 373 ADCRL: 8-bit A/D conversion result register L ...........................................................................................
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78K0/Ix2 APPENDIX B REGISTER INDEX [F] FPCTL: Self programming mode control register ................................................................................................ 665 [H] HIZTREN: High-impedance output function enable register.................................................................................... 245 HIZTRS: High-impedance output mode select register.........................................................................................
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78K0/Ix2 APPENDIX B REGISTER INDEX P7: Port register 7 ........................................................................................................................................ 136 P12: Port register 12 ...................................................................................................................................... 136 PCC: Processor clock control register .............................................................................................................
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78K0/Ix2 APPENDIX B REGISTER INDEX TX0CTL0: 16-bit timer X0 operation control register 0 ............................................................................................ 192 TX0CTL1: 16-bit timer X0 operation control register 1 ............................................................................................ 194 TX0CTL2: 16-bit timer X0 operation control register 2 ............................................................................................
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78K0/Ix2 APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition Page Description Classification Throughout   Update of URL CHAPTER 6 16-BIT TIMERS X0 AND X1 p. 207-215 Addition of 6.4 Operation of 16-Bit Timer/Event Counter 00 p. 216, 218,  Duty = (Set value of TXnCR1 219, 224, 225 p.
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78K0/Ix2 APPENDIX C REVISION HISTORY C.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
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78K0/Ix2 APPENDIX C REVISION HISTORY (2/7) Edition 3rd Edition Description Chapter Modification of Related Documents INTRODUCTION Modification of description in 1.1 Features CHAPTER 1 OUTLINE Modification of [Port Number] and [Example of Port Number] in 1.2 Ordering Information Modification of description in 1.5 Outline of Functions Modification of description of RESET pin Addition of Caution 2 to 2.2.5 P70 (port 7) CHAPTER 2 PIN FUNCTIONS Addition of Caution to 2.2.
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78K0/Ix2 APPENDIX C REVISION HISTORY (3/7) Edition 3rd Edition Description Modification of 6.4 (1) PWM output operation (single output) to (4) PWM output operation (TMX0 and TMX1 synchronous start mode) Chapter CHAPTER 6 16-BIT TIMERS X0 AND X1 Addition of Notes 1, 2 to Figure 6-34 Block Diagram of 16-Bit Timer X0 Output Configuration to Figure 6-36. Block Diagram of 16-Bit Timers X0 and X1 Output Configuration Modification of 6.
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78K0/Ix2 APPENDIX C REVISION HISTORY (4/7) Edition Description 3rd Edition Addition of Note to Figure 13-13 Example of Setting Procedure when Starting Comparator Operation (Using Input Voltage from Comparator Common (CMPCOM) Pin for Comparator Reference Voltage (78K0/IB2 only)) Chapter CHAPTER 13 COMPARATORS Modification of Figure 13-14 Example of Setting Procedure when Stopping Comparator Operation Addition of the port output mode register 6 (POM6) to Table 14-1 Configuration of Serial Interface UAR
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78K0/Ix2 APPENDIX C REVISION HISTORY (5/7) Edition 3rd Edition Description Modification of (4) 0083H/1083H in 24.1 Functions of Option Bytes Modification of Figure 24-1. Format of Option Byte (3/3) Modification of Figure 25-2 Environment for Writing Program to Flash Memory Modification of Table 25-2 Pin Connection Chapter CHAPTER 24 OPTION BYTE CHAPTER 25 FLASH MEMORY Modification of 25.4.1 TOOL pins Addition of 25.4.7 On-board writing when connecting crystal/ceramic resonator Modification of 25.5.
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78K0/Ix2 APPENDIX C REVISION HISTORY (6/7) Edition 4th Edition Description Deletion of Caution of (2) Control mode in 2.2.4 P60 and P61 (port 6) Addition of Note 3 to Table 2-2. Pin I/O Circuit Types (78K0/IY2) to Table 2-4. Pin I/O Circuit Types (78K0/IB2 (30 Pins)) Chapter CHAPTER 2 PIN FUNCTIONS Change of Table 2-3. Pin I/O Circuit Types (78K0/IA2) and Table 2-4. Pin I/O Circuit Types (78K0/IB2 (30 Pins)) Change of FLMDPUP bit to a reserved word in Table 3-6.
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78K0/Ix2 APPENDIX C REVISION HISTORY (7/7) Edition 4th Edition Description Chapter Addition of (2) When using the TOOLC0 and TOOLD0 pins (with X1/X2 oscillator is used, both debugging and programming are performed) to Figure 26-1.
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78K0/Ix2 User’s Manual: Hardware Publication Date: Rev.0.01 Rev.5.
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http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
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78K0/Ix2 R01UH0010EJ0500