Datasheet

78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 78
Sep 27, 2010
Figure 3-12. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
Register pair lower
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
Register pair higher
FEDEH
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
PC15 to PC8
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
PC7 to PC0
FEDEH
(c) Interrupt, BRK instructions (when SP = FEE0H)
PC15 to PC8
PSW
FEDFH
FEE0H
SP
SP
FEE0H
FEDEH
FEDDH
PC7 to PC0
FEDDH