Datasheet

78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 68
Sep 27, 2010
Figure 3-4. Memory Map ( μ PD78F0573, 78F0578, 78F0583, 78F0588)
Data memory
space
Program
memory space
Flash memory
32768 × 8 bits
0000H
8000H
7FFFH
FB00H
FAFFH
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Reserved
Internal high-speed RAM
1024 × 8 bits
General-purpose
registers
32 × 8 bits
Special function registers
(SFR)
256 × 8 bits
7FFFH
Program area
1905 × 8 bits
Program area
On-chip debug security
ID setting area
Note 1
10 × 8 bits
Option byte area
Note 1
5 × 8 bits
CALLF entry area
2048 × 8 bits
Program area
0800H
07FFH
1000H
0FFFH
1080H
107FH
1085H
1084H
108FH
108EH
Boot cluster 1
Vector table area
64 × 8 bits
CALLT table area
64 × 8 bits
Option byte area
Note 1
5 × 8 bits
On-chip debug security
ID setting area
Note 1
10 × 8 bits
0040H
003FH
0000H
0085H
0084H
0080H
007FH
008FH
008EH
1FFFH
Boot cluster 0
Note 2
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs
to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6 Security
Settings).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 00H
Block 01H
Block 1FH
1 KB
7FFFH
07FFH
0000H
0400H
03FFH
7C00H
7BFFH
0800H