Datasheet

78K0/Kx2-L CHAPTER 31 CAUTIONS FOR WAIT
R01UH0028EJ0400 Rev.4.00 778
Sep 27, 2010
CHAPTER 31 CAUTIONS FOR WAIT
31.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may
be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing,
until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution
clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table 31-1). This
must be noted when real-time processing is performed.