Datasheet

78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 65
Sep 27, 2010
Figure 3-1. Memory Map ( μ PD78F0550, 78F0555, 78F0560, 78F0565)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FD80H
FD7FH
1000H
0FFFH
0000H
Flash memory
4096 × 8 bits
Program
memory space
Reserved
Vector table area
64 × 8 bits
0040H
003FH
0000H
0085H
0084H
0080H
007FH
008FH
008EH
0800H
07FFH
0FFFH
CALLF entry area
2048 × 8 bits
Program area
1905 × 8 bits
On-chip debug security
ID setting area
10 × 8 bits
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
Internal high-speed RAM
384 × 8 bits
General-purpose
registers
32 × 8 bits
Special function registers
(SFR)
256 × 8 bits
Boot cluster 0
Note
Data memory
space
Note Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6 Security Settings).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 00H
Block 01H
Block 03H
Block 02H
1 KB
0FFFH
07FFH
0000H
0400H
03FFH
0C00H
0800H
0BFFH