Datasheet

78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0028EJ0400 Rev.4.00 759
Sep 27, 2010
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(c) CSI1n (master mode, SCK1n... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 200 ns SCK1n cycle time tKCY1
1.8 V ≤ V
DD < 2.7 V 400 ns
SCK1n high-/low-level width
t
KH1,
t
KL1
t
KCY1/2 − 10
Note 1
ns
SI1n setup time (to SCK1n↑) tSIK1 30 ns
SI1n hold time (from SCK1n↑) tKSI1 30 ns
Delay time from SCK1n↓ →to
SO1n output
t
KSO1 C = 50 pF
Note 2
40 ns
Notes 1. This value is when high-speed system clock (f
XH) is used.
2. C is the load capacitance of the SCK1n and SO1n output lines.
(d) CSI1n (slave mode, SCK1n... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1n cycle time tKCY2 400 ns
SCK1n high-/low-level width
t
KH2,
t
KL2
t
KCY2/2 ns
SI1n setup time (to SCK1n↑) tSIK2 80 ns
SI1n hold time (from SCK1n↑) tKSI2 50 ns
Delay time from SCK1n↓ →to
SO1n output
t
KSO2 C = 50 pF
Note
120 ns
Note C is the load capacitance of the SO1n output line.
Remark n = 0, 1