Datasheet

78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS
R01UH0028EJ0400 Rev.4.00 57
Sep 27, 2010
Table 2-5. Pin I/O Circuit Types (78K0/KB2-L)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000
P01/TO00/TI010
5-AQ
P10/ANI8/ANP1-
Note 1
/SCK10 11-L
P11/ANI9/ANP1OUT
Note 1
/SI10 11-M
P12/ANI10/ANP1+
Note 1
/SO10 11-K
P13/TxD6 5-AG
P14/RxD6 5-AQ
P15/TOH0 5-AG
P16/TOH1/INTP5
P17/TI50/TO50
5-AQ
Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
ANI0/P20/AMP0-
Note 1
11-P
ANI1/P21/AMP0OUT
Note 1
/
PGAIN
Note 1
11-O
ANI2/P22/AMP0+
Note 1
11-N
ANI3/P23 11-G
<Digital input setting>
Independently connect to AV
REF or AVSS via a resistor.
<Digital output setting and analog input setting>
Leave open.
Note 2
P30/INTP1
P31/INTP2/TOOLC1
P32/INTP3/TOOLD1
P33/TI51/TO51/INTP4
5-AQ Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
P60/SCLA0/INTP11
P61/SDAA0/INTP10
5-AS Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
P120/EXLVI/INTP0
5-AQ
I/O
P121/X1/TOOLC0
Note 3
P122/X2/EXCLK/TOOLD0
Note 3
37-A Input
Independently connect to V
DD or VSS via a resistor.
RESET/P125 42-A Input Connect directly to VDD or via a resistor.
AVREF
− −
Connect directly to VDD.
Note 4
AVSS
− −
Connect directly to VSS.
Notes 1.
μ PD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
4. When port 2 is used as the digital port pins, make AV
REF the same potential as VDD.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the analog
input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and P12/ANI10/AMP1+/SO10 are set
in the digital input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the high
level.
<R>
<R>
<R>