Datasheet
78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS
R01UH0028EJ0400 Rev.4.00 56
Sep 27, 2010
Table 2-4. Pin I/O Circuit Types (78K0/KA2-L (25-pin and 32-pin products))
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00
Note 1
/TI000
Note 1
/
INTP0
Note 1
P01
Note 2
/TO00
Note 2
/
TI010
Note 2
P02/SSI11/INTP5
5-AQ Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
ANI0/P20/AMP0-
Note 3
11-P
ANI1/P21/AMP0OUT
Note 3
/
PGAIN
Note 3
11-O
ANI2/P22/AMP0+
Note 3
11-N
ANI3/P23 to ANI6/P26
ANI7/P27
Note 2
11-G
<Digital input setting>
Independently connect to AV
REF or VSS via a resistor.
<Digital output setting and analog input setting >
Leave open.
Note 4
P31/INTP2/TOOLC1
P32/TOH1/INTP3/TOOLD1
P33
P34/INTP4
(/TOH1)(/TI51)
Note 1
P35/SCK11
P36/SI11
P37/SO11
5-AQ Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
P60/SCLA0/TxD6
P61/SDAA0/RxD6
5-AS Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
ANI8
Note 2
/P70
Note 2
ANI9
Note 2
/P71
Note 2
ANI10
Note 2
/P72
Note 2
11-G
I/O
<Digital input setting>
Independently connect to AVREF or VSS via a resistor.
<Digital output setting and analog input setting >
Leave open.
Note 4
P121/X1/TOOLC0
Note 5
(/TI000)(/INTP0)
P122/X2/EXCLK/
TOOLD0
Note 5
37-A Independently connect to V
DD or VSS via a resistor.
RESET/P125
(/TI000)
Note 2
(/INTP0)
Note 2
42-A
Input
Connect directly to V
DD or via a resistor.
AVREF
− −
Connect directly to VDD.
Notes 1. 25-pin products only
2. 32-pin products only
3.
μ
PD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
4. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
5. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, ANI3/P23 to ANI5/P25, and ANI8/P70
to ANI10/P72 are set in the analog input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset signal
is generated during low level input, the reset status continues until the input rises to the high level.
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