Datasheet

78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR
R01UH0028EJ0400 Rev.4.00 682
Sep 27, 2010
Figure 22-7. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 1)
V EXLVI
Set LVI to be
used for reset
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
Note 3
LVI reset signal
Internal reset signal
LVION flag
(set by software)
LVIMD flag
(set by software)
LVISEL flag
(set by software)
<1>
<2>
<3>
<4> Wait time
<5>
<6>
Note 2
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Cleared by
software
Cleared by
software
Time
H
Note 1
Input voltage from
external input pin (EXLVI)
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 20 RESET
FUNCTION.
Remark <1> to <6> in Figure 22-7 above correspond to <1> to <6> in the description of “When starting operation” in
22.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).