Datasheet

78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR
R01UH0028EJ0400 Rev.4.00 676
Sep 27, 2010
(3) Port mode register 12 (PM12) (78K0/KB2-L and 78K0/KC2-L only)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time,
the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 22-4. Format of Port Mode Register 12 (PM12) (78K0/KB2-L and 78K0/KC2-L only)
0
PM120
1
1
2
1
3
1
4
1
5
1
6
1
7
1
Symbol
PM12
Address: FF2CH After reset: FFH R/W
PM120 P120 pin I/O mode selection
0 Output mode (output buffer on)
1 Input mode (output buffer off)
22.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
(1) Used as reset (LVIMD = 1)
• If LVISEL = 0, compares the supply voltage (V
DD) and LVI detection voltage (VLVI), generates an internal reset
signal when VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and LVI detection voltage (V
EXLVI),
generates an internal reset signal when EXLVI < V
EXLVI, and releases internal reset when EXLVI ≥ VEXLVI.
Remarks 1. The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to
raise the power supply from the POC detection voltage (V
POR = 1.61 V (TYP.)) or lower, the internal
reset signal is generated when the supply voltage (VDD) < detection voltage (VLVI = 1.91 V ±0.1 V).
2. Level detection of input voltage from external input pin (EXLVI) is available only in 78K0/KB2-L and
78K0/KC2-L.
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