Datasheet

78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS
R01UH0028EJ0400 Rev.4.00 55
Sep 27, 2010
Table 2-3. Pin I/O Circuit Types (78K0/KA2-L (20-pin products))
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000/INTP0
P01/TO00/TI010
5-AQ Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
ANI0/P20/AMP0-
Note 1
11-P
ANI1/P21/AMP0OUT
Note 1
/
PGAIN
Note 1
11-O
ANI2/P22/AMP0+
Note 1
11-N
ANI3/P23
ANI4/P24
ANI5/P25
11-G
<Digital input setting>
Independently connect to AV
REF or VSS via a resistor.
<Digital output setting and analog input setting >
Leave open.
Note 2
P30/TOH1/TI51/INTP1
P31/INTP2/TOOLC1
P32/TOH1/INTP3/TOOLD1
5-AQ Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave open.
P60/SCLA0/TxD6
P61/SDAA0/RxD6
5-AS
I/O
Input: Independently connect to V
DD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
P121/X1/TOOLC0
Note 3
P122/X2/EXCLK/TOOLD0
Note 3
37-A Input
Independently connect to V
DD or VSS via a resistor.
RESET/P125 42-A Input Connect directly to VDD or via a resistor.
AVREF
− −
Connect directly to VDD.
Notes 1. μ PD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI5/P25 are set in
the analog input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the high
level.
<R>
<R>
<R>