Datasheet

78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR
R01UH0028EJ0400 Rev.4.00 673
Sep 27, 2010
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
<0>
LVIF
<1>
LVIMD
<2>
LVISEL
Note 5
3
0
4
0
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FFBEH After reset: 00H
Note 1
R/W
Note 2
LVION
Notes 3, 4
Enables low-voltage detection operation
0 Disables operation
1 Enables operation
LVISEL
Notes 3, 5
Voltage detection selection
0 Detects level of supply voltage (VDD)
1 Detects level of input voltage from external input pin (EXLVI)
LVIMD
Note 3
Low-voltage detection operation mode (interrupt/reset) selection
0 • LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops
lower than the LVI detection voltage (V
LVI) (VDD < VLVI) or when VDD
becomes V
LVI or higher (VDD ≥ VLVI).
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the LVI detection voltage (V
EXLVI)
(EXLVI < V
EXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥
V
EXLVI).
1 • LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) < the
LVI detection voltage (V
LVI) and releases the reset signal when VDD ≥ VLVI.
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < the LVI detection voltage (V
EXLVI) and
releases the reset signal when EXLVI ≥ V
EXLVI.
LVIF Low-voltage detection flag
0 • LVISEL = 0: Supply voltage (VDD) ≥ LVI detection voltage (VLVI), or when LVI operation
is disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ LVI detection voltage
(V
EXLVI), or when LVI operation is disabled
1 • LVISEL = 0: Supply voltage (VDD) < LVI detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < LVI detection voltage
(V
EXLVI)
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVI resets (except resets by the LVI default start function).
The value of this register is reset to “00H” by other resets.
2. Bit 0 is read-only.
3. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not
cleared to 0 in the case of an LVI reset.
4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for
an operation stabilization time (10
μ s (MAX.)) from when LVION is set to 1 until operation is stabilized.
After the operation stabilizes, an external input (minimum pulse width: 200
μ s) of 200 μ s or more is
required until LVIF is set (1) after the voltage drops to the LVI detection voltage or less.
5. 78K0/KB2-L and 78K0/KC2-L only.
<R>