Datasheet

78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT
R01UH0028EJ0400 Rev.4.00 668
Sep 27, 2010
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) When LVI is ON upon power application (option byte: LVISTART = 1)
0 V
Supply voltage
(V
DD )
1.8 V
Note 1
V
PDR = 1.59 V (TYP.)
V
LVI
V
POR = 1.61 V (TYP.)
V
LVI = 1.91 V (TYP.)
Internal high-speed
oscillation clock (f
IH)
High-speed
system clock (f
XH)
(when X1 oscillation
is selected)
Operation
stops
CPU
Internal reset signal
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Note 3
POC processing time
(0.93 to 3.7 ms)
Reset processing time
(12 to 51 μs)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Reset
period
(oscillation
stop)
Reset processing time
(12 to 51 μs)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Reset
period
(oscillation
stop)
Note 3
POC processing time
(0.93 to 3.7 ms)
Reset processing time
(12 to 51 μs)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Operation stops
Starting oscillation is
specified by software
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Set LVI to be
used for reset
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
2. The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected as
the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
3. The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
normal operation.
• When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is less than 3.7 ms:
A POC processing time of about 1.0 to 3.8 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
• When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is greater than 3.7 ms:
A reset processing time of about 12 to 51
μ s is required between reaching 1.91 V (TYP.) and starting
normal operation.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
V
POR: POC power supply rise detection voltage
V
PDR: POC power supply fall detection voltage
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