Datasheet

78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT
R01UH0028EJ0400 Rev.4.00 667
Sep 27, 2010
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) When LVI is OFF upon power application (option byte: LVISTART = 0)
Internal high-speed
oscillation clock (f
IH )
High-speed
system clock (f
XH )
(when X1 oscillation
is selected)
Starting oscillation is
specified by software
V PDR = 1.59 V (TYP.)
V
LVI
Operation
stops
V POR = 1.61 V (TYP.)
Starting oscillation is
specified by software
CPU
0 V
Supply voltage
(V
DD )
1.8 V
Note 1
0.5 V/ms (MIN.)
Note 2
Starting oscillation is
specified by software
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Note 3
Reset processing (12 to 51 μs)
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Normal operation
(internal high-speed
oscillation clock)
Note 4
Operation stops
Reset
period
(oscillation
stop)
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Normal operation
(internal high-speed
oscillation clock)
Note 4
Reset processing
(12 to 51 μs)
Internal reset signal
Wait for voltage
stabilization
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Note 3
(0.93 to 3.7 ms)
Reset processing
(12 to 51 μs)
Wait for voltage
stabilization
(0.93 to 3.7 ms)
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
2. If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V.
3. The internal voltage stabilization wait time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4. The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected as
the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
VPOR: POC power supply rise detection voltage
V
PDR: POC power supply fall detection voltage