Datasheet

78K0/Kx2-L CHAPTER 20 RESET FUNCTION
R01UH0028EJ0400 Rev.4.00 659
Sep 27, 2010
Table 20-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fIH Operation stopped
fX Operation stopped (X1 and X2 pins are input port mode)
Main system clock
fEXCLK Clock input invalid (EXCLK pin is input port mode)
fXT Operation stopped (XT1 and XT2 pins are input port mode)
Subsystem clock
fEXCLKS Clock input invalid (EXCLKS pin is input port mode)
fIL
CPU
Flash memory
Operation stopped
RAM
Operation stopped (The value, however, is retained when the voltage is at least the power-
onclear detection voltage.)
Port (latch)
16-bit timer/event counter 00
50
8-bit timer/event
counter
51
H0 8-bit timer
H1
Real-time counter (RTC)
Watchdog timer
Clock output
A/D converter
Operational amplifier 0 (AMP0,
PGA)
Operational amplifier 1 (AMP1)
UART6
CSI10
CSI11
Serial interface
IICA
External interrupt
Key interrupt
Operation stopped
Power-on-clear function Operable
Low-voltage detection function Operation stopped (however, operation continues at LVI reset)
On-chip debug function Operation stopped
Remarks 1. f
IH: Internal high-speed oscillation clock, fX: X1 clock
f
EXCLK: External main system clock, fXT: XT1 clock
f
EXCLKS: External subsystem clock, fIL: Internal low-speed oscillation clock
2. The functions mounted depend on the product. Refer to 1.4 Block Diagram and 1.5 Outline of
Functions.