Datasheet

78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION
R01UH0028EJ0400 Rev.4.00 647
Sep 27, 2010
Figure 19-4. HALT Mode Release by Reset (2/2)
(3) When subsystem clock is used as CPU clock
Note1
HALT
instruction
Reset signal
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Reset
period
Normal operation mode
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation
stopped
Starting XT1 oscillation is
specified by software.
Reset
processing
(12 to 51 μs)
Oscillation stabilization time
(measure by the user)
Note 2
Notes 1. 78K0/KC2-L only
2. Oscillation stabilization time is not required when using the external subsystem clock (f
EXCLKS) as the
subsystem clock.
Table 19-2. Operation in Response to Interrupt Request in HALT Mode
Release Source MK×× PR×× IE ISP Operation
0 0 0
×
Next address
instruction execution
0 0 1
×
Interrupt servicing
execution
0 1 0 1
0 1
×
0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1
× × ×
HALT mode held
Reset
− − × ×
Reset processing
×: don’t care
19.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.