Datasheet

78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS

R01UH0028EJ0400 Rev.4.00 619

Sep 27, 2010

Figure 17-22. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)

(48-pin products of 78K0/KC2-L)

Address: FFE8H After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>

PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR

Address: FFE9H After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>

PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 CSIPR10 STPR6 SRPR6

Address: FFEAH After reset: FFH R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>

PR1L PPR8 PPR7 RTCPR KRPR TMPR51 RTCIPR PPR6 ADPR

Address: FFEBH After reset: FFH R/W

Symbol 7 6 5 <4> <3> <2> <1> <0>

PR1H 1 1 1 PPR11 PPR10 PPR9 CSIPR11 IICAPR0

XXPRX Priority level selection

0 High priority level

1 Low priority level

Caution Be sure to set bits 5 to 7 of PR1H to 1.

(4) External interrupt rising edge enable registers (EGPCTL0, EGPCTL1), external interrupt falling edge enable

registers (EGNCTL0, EGNCTL1)

These registers specify the valid edge for INTPn.

EGPCTL0, EGPCTL1, EGNCTL0, and EGNCTL1 are set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears these registers to 00H.

Remark n = 0, 1: 78K0/KY2-L

n = 0 to 3: 20-pin products of 78K0/KA2-L

n = 0, 2 to 5: 25, 32-pin products of 78K0/KA2-L

n = 0 to 5, 10, 11: 78K0/KB2-L

n = 0 to 5, 9 to 11: 40-pin products of 78K0/KC2-L

n = 0 to 5, 8 to 11: 44-pin products of 78K0/KC2-L

n = 0 to 11: 48-pin products of 78K0/KC2-L

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