Datasheet

78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 613
Sep 27, 2010
(3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and
PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Figure 17-16. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KY2-L)
Address: FFE8H After reset: FFH R/W
Symbol <7> 6 5 4 3 <2> <1> <0>
PR0L SREPR6 1 1 1 1 PPR1 PPR0 LVIPR
Address: FFE9H After reset: FFH R/W
Symbol <7> <6> 5 4 <3> 2 <1> <0>
PR0H TMPR010 TMPR000 1 1 TMPRH1 1 STPR6 SRPR6
Address: FFEAH After reset: FFH R/W
Symbol 7 6 5 4 <3> 2 1 <0>
PR1L 1 1 1 1 TMPR51 1 1 ADPR
Address: FFEBH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 <0>
PR1H 1 1 1 1 1 1 1 IICAPR0
XXPRX Priority level selection
0 High priority level
1 Low priority level
Caution Be sure to set bits 3 to 6 of PR0L, bits 2, 4 and 5 of PR0H, bits 1, 2, 4 to 7 of PR1L, and bits 1 to 7 of
PR1H to 1.