Datasheet

78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 592
Sep 27, 2010
Table 17-1. Interrupt Source List (1/2)
Interrupt Source
KY
2-L
KA2-L
KB
2-L
KC2-L
Interrupt
Type
Internal/
External
Basic
Configuration
Type
Note 1
Default
Priority
Note 2
Name Trigger
Vector
Table
Address
16
pin
s
20
pin
s
25,
32
pin
s
30
pin
s
40p
ins
44
pin
s
48
pin
s
Internal (A) 0 INTLVI Low-voltage detection
Note 3
0004H
√ √ √ √ √ √ √
1 INTP0 0006H
√ √ √ √ √ √ √
2 INTP1 0008H
√ √ − √ √ √ √
3 INTP2 000AH
− √ √ √ √ √ √
4 INTP3 000CH
− √ √ √ √ √ √
5 INTP4 000EH
− − √ √ √ √ √
External (B)
6 INTP5
Pin input edge detection
0010H
− − √ √ √ √ √
7 INTSRE6 UART6 reception error generation 0012H
√ √ √ √ √ √ √
8 INTSR6 End of UART6 reception 0014H
√ √ √ √ √ √ √
9 INTST6 End of UART6 transmission 0016H
√ √ √ √ √ √ √
INTCSI10 End of CSI10 communication 0018H
− − − √ √ √ √
10
INTCSI11 End of CSI11 communication 0018H
− − √ − − − −
11 INTTMH1
Match between TMH1 and CMP01
(when compare register is specified)
001AH
√ √ √ √ √ √ √
12 INTTMH0
Match between TMH0 and CMP00
(when compare register is specified)
001CH
− − − √ √ √ √
13 INTTM50
Match between TM50 and CR50
(when compare register is specified)
001EH
− − − √ √ √ √
14 INTTM000
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
0020H
√ √ √ √ √ √ √
15 INTTM010
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
0022H
√ √ √ √ √ √ √
Internal (A)
16 INTAD End of A/D conversion 0024H
√ √ √ √ √ √ √
External (B) 17 INTP6 Pin input edge detection 0026H
− − − − − − √
18 INTRTCI
Interval signal detection of real-time
counter
0028H
− − − − √ √ √
Maskable
Internal (A)
19
INTTM51
Note 4
Match between TM51 and CR51
(when compare register is specified)
002AH
√ √ √ √ √ √ √
Notes 1. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
2. The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
4. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon the
timing when the INTTM5H1 signal is generated (refer to Figure 8-14 Transfer Timing).
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