Datasheet

78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
R01UH0028EJ0400 Rev.4.00 585
Sep 27, 2010
Figure 16-16. Timing of Clock/Data Phase
(a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(c) Type 3: CKP1n = 1, DAP1n = 0, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(d) Type 4: CKP1n = 1, DAP1n = 1, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
Remarks 1. 78K0/KA2-L (25, 32-pin products): n = 1
78K0/KB2-L: n = 0
78K0/KC2-L: n = 0, 1
2. The above figure illustrates a communication operation where data is transmitted with the MSB first.