Datasheet

78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
R01UH0028EJ0400 Rev.4.00 571
Sep 27, 2010
Figure 16-7. Format of Serial Clock Selection Register 11 (CSIC11)
(78K0/KA2-L (25, 32-pin products), 78K0/KC2-L)
Address: FF89H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110
CKP11 DAP11 Specification of data transmission/reception timing Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
4
CSI11 serial clock selection
Note 1
CKS112 CKS111 CKS110
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
Mode
0 0 0 fPRS/2 1 MHz 2.5 MHz
5 MHz
0 0 1 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
0 1 0 fPRS/2
3
250 kHz 625 kHz 1.25 MHz
0 1 1 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
1 0 0 fPRS/2
5
62.5 kHz 156.25 kHz 312.5 kHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
1 1 0 fPRS/2
7
15.63 kHz 39.06 kHz 78.13 kHz
Master mode
1 1 1 External clock input from SCK11
Note 2
Slave mode
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. Do not start communication with the external clock from the SCK11 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.