Datasheet

78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
R01UH0028EJ0400 Rev.4.00 570
Sep 27, 2010
Note 2. Do not start communication with the external clock from the SCK10 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
2. To use P10/SCK10 and P12/SO10 as general-purpose ports, set CSIC10 in the default status (00H).
3. The phase type of the data clock is type 1 after reset.
Remark f
PRS: Peripheral hardware clock frequency