Datasheet

78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
R01UH0028EJ0400 Rev.4.00 569
Sep 27, 2010
(2) Serial clock selection register 1n (CSIC1n)
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Remark 78K0/KA2-L (25, 32-pin products): n = 1
78K0/KB2-L: n = 0
78K0/KC2-L: n = 0, 1
Figure 16-6. Format of Serial Clock Selection Register 10 (CSIC10) (78K0/KB2-L and 78K0/KC2-L)
Address: FF81H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100
CKP10 DAP10 Specification of data transmission/reception timing Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
4
CSI10 serial clock selection
Note 1
CKS102 CKS101 CKS100
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
Mode
0 0 0 fPRS/2 1 MHz 2.5 MHz 5 MHz
0 0 1 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
0 1 0 fPRS/2
3
250 kHz 625 kHz 1.25 MHz
0 1 1 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
1 0 0 fPRS/2
5
62.5 kHz 156.25 kHz 312.5 kHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
1 1 0 fPRS/2
7
15.63 kHz 39.06 kHz 78.13 kHz
Master mode
1 1 1 External clock input from SCK10
Note 2
Slave mode
Note 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz