Datasheet

78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA
R01UH0028EJ0400 Rev.4.00 534
Sep 27, 2010
15.5.17 Timing of I
2
C interrupt request (INTIICA0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the
IICAS0 register when the INTIICA0 signal is generated are shown below.
Remark ST: Start condition
AD6 to AD0: Address
R/W: Transfer direction specification
ACK: Acknowledge
D7 to D0: Data
SP: Stop condition