Datasheet

78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA
R01UH0028EJ0400 Rev.4.00 506
Sep 27, 2010
15.4.2 Setting transfer clock by using IICWL and IICWH registers
(1) Setting transfer clock on master side
Transfer clock =
f
PRS
IICWL + IICWH + fPRS (tR + tF)
At this time, the optimal setting values of the IICWL and IICWH registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL =
0.52
Transfer clock
× fPRS
IICWH = (
0.48
Transfer clock
− tR − tF) × fPRS
• When the normal mode
IICWL =
0.47
Transfer clock
× fPRS
IICWH = (
0.53
Transfer clock
− tR − tF) × fPRS
(2) Setting IICWL and IICWH on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL = 1.3
μ s × fPRS
IICWH = (1.2 μ s − tR − tF) × fPRS
• When the normal mode
IICWL = 4.7
μ s × fPRS
IICWH = (5.3
μ s − tR − tF) × fPRS
Caution Note the minimum f
PRS operation frequency when setting the transfer clock. The minimum fPRS
operation frequency for serial interface IICA is determined according to the mode.
Fast mode: f
PRS = 3.5 MHz (min.)
Normal mode: f
PRS = 1 MHz (min.)
Remarks 1. Calculate the rise time (t
R) and fall time (tF) of the SDA0 and SCLA0 signals separately, because they
differ depending on the pull-up resistance and wire load.
2. IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
t
F: SDAA0 and SCLA0 signal falling times (refer to CHAPTER 28 ELECTRICAL
SPECIFICATIONS)
t
R: SDAA0 and SCLA0 signal rising times (refer to CHAPTER 28 ELECTRICAL
SPECIFICATIONS)
f
PRS: Peripheral hardware clock frequency