Datasheet

78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA
R01UH0028EJ0400 Rev.4.00 504
Sep 27, 2010
(8) Port output mode register 6 (POM6)
This register sets the output mode of P60 to P63 in 1-bit units. During I
2
C communication, set POM60 and POM61 to
1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-12. Format of Port Output Mode Register 6 (POM6)
Address: FF2AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM6 0 0 0 0
POM63
Note
POM62
Note
POM61 POM60
POM6n P6n pin output mode selection (n = 0 to 3)
0 Normal output (CMOS output) mode
1 N-ch open drain output (VDD tolerance) mode
Note 78K0/KC2-L only
(9) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61 to 0,
and set the output latches of P60 and P61 to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 15-13. Format of Port Mode Register 6 (PM6)
PM60PM61PM62PM631111
P6n pin I/O mode selection (n = 0 to 3)
Output mode (output buffer on)
Input mode (output buffer off)
PM6n
0
1
01234567
PM6
Address: FF26H After reset: FFH R/W
Symbol
Remark The figure shown above presents the format of port mode register 6 of the 78K0/KC2-L. For
the format of port mode register 6 of other products, refer to (1) Port mode registers (PMxx)
in 4.3 Registers Controlling Port Function.